Electrostatic discharge protection semiconductor device

Abstract

An ESD protection semiconductor device is disclosed. The ESD protection semiconductor device includes a substrate and a gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins are formed in the substrate respectively at two sides of the gate set. At least a first doped fin is formed in the substrate at one side of the gate set the same as the source fins. A plurality of isolation structures are formed in one of the drain fins to define at least a second doped fin in the one of the drain fins. The source fins and the drain fins are of a first conductivity type. The first doped fin is of a second conductivity type that is complementary to the first conductivity type. The first doped fin and the second doped fin are electrically connected to each other.

What is claimed is: 
     
       1. An ESD protection semiconductor device, comprising:
 a substrate; 
 a gate set disposed on the substrate; 
 a plurality of source fins and a plurality of drain fins disposed in the substrate respectively at two sides of the gate set, wherein the source fins and the drain fins comprise a first conductivity type; 
 a first doped fin disposed in the substrate at one side of the gate set the same as the source fins and being spaced apart from the source fins and is positioned in between the source fins, wherein the first doped fin comprises a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other; 
 a second doped fin disposed in the substrate at one side of the gate set the same as the drain fins and spaced apart from the drain fins, wherein the second doped fin comprises the first conductivity type; and 
 a plurality of isolation structures disposed in the second doped fin to define a single doped region in the second doped fin, wherein the single doped region is electrically connected to the first doped fin. 
 
     
     
       2. The ESD protection semiconductor device according to  claim 1 , wherein the source fins are electrically connected to a ground pad, and the drain fins are electrically connected to an IO pad. 
     
     
       3. The ESD protection semiconductor device according to  claim 1 , wherein the source fins and the drain fins extend along a first direction and are arranged in parallel along a second direction, wherein the first direction and the second direction are perpendicular. 
     
     
       4. The ESD protection semiconductor device according to  claim 3 , wherein the first doped fin extends along the first direction. 
     
     
       5. The ESD protection semiconductor device according to  claim 3 , further comprising at least a contact plug disposed on the substrate, extending along the second direction and overlapping on the drain fins to electrically connect to the drain fins. 
     
     
       6. The ESD protection semiconductor device according to  claim 5 , wherein the contact plug overlaps a region of the second doped fin that is electrically isolated from the single doped region by the isolation structures. 
     
     
       7. The ESD protection semiconductor device according to  claim 3 , further comprising at least a contact plug disposed on the substrate, extended along the second direction and overlapping on the source fins to electrically connect to the source fins. 
     
     
       8. The ESD protection semiconductor device according to  claim 7 , wherein the contact plug connected to the source fins does not overlap the first doped fin. 
     
     
       9. The ESD protection semiconductor device according to  claim 1 , wherein the first doped fin and the single doped region are electrically connected by a metal layer. 
     
     
       10. The ESD protection semiconductor device according to  claim 1 , wherein the substrate comprises the second conductivity type. 
     
     
       11. The ESD protection semiconductor device according to  claim 1 , wherein the single doped region comprises the first conductivity type. 
     
     
       12. The ESD protection semiconductor device according to  claim 11 , wherein the drain fins, the substrate under the isolation structure and the single doped region construct a bipolar junction transistor (BJT). 
     
     
       13. The ESD protection semiconductor device according to  claim 12 , a current direction of the bipolar junction transistor is parallel with the drain fins. 
     
     
       14. The ESD protection semiconductor device according to  claim 1 , further comprising another isolation structure formed in the substrate to electrically isolate the plurality of source fins and the plurality of drain fins.