Semiconductor device manufacturing method

Abstract

A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a wiring substrate comprising a first surface; 
 a stacked body on the first surface, the stacked body comprising a first chip, a second chip between the first chip and the first surface, and a third chip between the second chip and the first surface, the second chip having a through via; 
 a first resin contacting the first surface and the second chip; 
 a second resin sealing the stacked body, a portion of the second resin being between the wiring substrate and the stacked body; and 
 a bump electrode electrically and physically connecting the wiring substrate and the stacked body, wherein 
 the bump electrode is at a distance further from a central portion of the wiring substrate than the first resin, and 
 the first and second resins are made of different materials. 
 
     
     
       2. The semiconductor device according  claim 1 , wherein the bump electrode is between the wiring substrate and the second chip. 
     
     
       3. The semiconductor device according to  claim 1 , wherein the first resin and a portion of the second resin is between the bump electrode and the third chip in a direction parallel to the first surface. 
     
     
       4. The semiconductor device according to  claim 1 , wherein the bump electrode comprises at least one of gold, nickel, copper, tin, bismuth, zinc, indium, aluminum, or palladium. 
     
     
       5. The semiconductor device according to  claim 1 , further comprising:
 an adhesive resin between the first, second, and third chips. 
 
     
     
       6. The semiconductor device according to  claim 1 , further comprising:
 a fourth chip on the stacked body. 
 
     
     
       7. The semiconductor device according to  claim 1 , wherein,
 the bump electrode electrically connects the second chip directly to the wiring substrate, 
 the first resin is between the bump electrode and the third chip in a direction parallel to the first surface, and 
 a portion of the second resin is between the first resin and the third chip in the direction parallel to the first surface. 
 
     
     
       8. A packaged semiconductor device, comprising:
 a wiring substrate having a first surface; 
 a first semiconductor chip having a second surface facing the first surface and a third surface opposite the second surface; 
 a bump electrode between the first semiconductor chip and the wiring substrate and contacting the second surface and the first surface; 
 a first adhesive between the first semiconductor chip and the wiring substrate and contacting the second surface and the first surface; 
 a second semiconductor chip on the third surface; 
 a support substrate on the second semiconductor chip, the second semiconductor chip between the support substrate and the first chip; 
 a third semiconductor chip on the second surface, the third semiconductor chip being between the first semiconductor chip and the wiring substrate, the first adhesive being between the third semiconductor chip and the bump electrode in a direction parallel to the first surface; and 
 a sealing resin covering the support substrate, the first semiconductor chip, the second semiconductor chip, the third semiconductor chip and the first surface of the wiring substrate, wherein 
 the sealing resin is between the first adhesive and the third semiconductor chip in the direction parallel to the first surface and between the third semiconductor chip and the first surface, and 
 the first adhesive and the sealing resin being different materials. 
 
     
     
       9. The packaged semiconductor device according to  claim 8 , further comprising:
 a plurality of solder balls on a surface of the wiring substrate opposite the first surface. 
 
     
     
       10. The packaged semiconductor device according to  claim 8 , further comprising:
 a fourth semiconductor chip between the second semiconductor chip and the support substrate. 
 
     
     
       11. The packaged semiconductor device according to  claim 8 , wherein
 the first and second semiconductor chips are memory chips, and 
 the third chip is a logic chip. 
 
     
     
       12. The packaged semiconductor device according to  claim 8 , wherein
 the first and second semiconductor chips are NAND flash memory chips, and 
 the third semiconductor chip is a LSI chip. 
 
     
     
       13. The packaged semiconductor device according to  claim 8 , wherein the second semiconductor chip includes a through-via. 
     
     
       14. The packaged semiconductor device according to  claim 8 , further comprising:
 a solder ball between the first and second semiconductor chips; 
 a second adhesive between the first and second semiconductor chips, wherein 
 the sealing resin is also between the first and second semiconductor chips. 
 
     
     
       15. The package semiconductor device according to  claim 8 , wherein the bump electrode comprises at least one of gold, nickel, copper, tin, bismuth, zinc, indium, aluminum, or palladium.