Self-aligned passivation of active regions

Abstract

A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).

What is claimed is: 
     
       1. A method comprising:
 forming a semiconductor region; 
 performing a first passivation process on the semiconductor region, wherein the first passivation process terminates dangling bonds at a first surface of the semiconductor region with a first species, and wherein the first species is selected from the group consisting of sulfur, selenium, and combination thereof; and 
 forming a gate stack on the passivated first surface of the semiconductor region. 
 
     
     
       2. The method of  claim 1 , wherein the first passivation process is performed to terminate the dangling bonds with sulfur. 
     
     
       3. The method of  claim 1 , wherein the first passivation process is performed to terminate the dangling bonds with selenium. 
     
     
       4. The method of  claim 1  further comprising performing a second passivation process on the semiconductor region to terminate dangling bonds at a second surface of the semiconductor region with a second species different from the first species. 
     
     
       5. The method of  claim 4 , wherein the first surface has a (001) or (100) surface plane, and the second surface has a (110) surface plane. 
     
     
       6. The method of  claim 4 , wherein the second species is selected from the group consisting of antimony, arsenic, and combinations thereof. 
     
     
       7. The method of  claim 1  further comprising performing a second passivation process on the semiconductor region to terminate dangling bonds at the first surface of the semiconductor region with a second species, wherein the first passivation process and the second passivation process are separate processes. 
     
     
       8. The method of  claim 1  further comprising:
 forming a dummy gate stack on the semiconductor region; 
 forming an Inter-Layer Dielectric (ILD) on opposite sides of the dummy gate stack; and 
 removing the dummy gate stack to leave a recess in the ILD, wherein the first surface is exposed to the recess, and the first passivation process is performed through the recess. 
 
     
     
       9. The method of  claim 1  further comprising:
 forming a dummy gate stack on the semiconductor region; 
 forming an Inter-Layer Dielectric (ILD) on opposite sides of the dummy gate stack; and 
 removing the dummy gate stack to leave a recess in the ILD, wherein the first passivation process is performed before the forming the dummy gate stack. 
 
     
     
       10. A method comprising:
 recessing isolation regions on opposite sides of a semiconductor region, wherein a top portion of the semiconductor region protrudes higher than the isolation regions to form a semiconductor fin; 
 attaching a first element to a surface of the semiconductor fin, wherein the first element is selected from the group consisting of sulfur, selenium, chlorine, and combinations thereof, and wherein the first element is attached through a liquid phase attachment process, with the first element comprised in a liquid; and 
 after the first element is attached to the surface of the semiconductor fin, forming a gate stack on the semiconductor fin. 
 
     
     
       11. The method of  claim 10 , wherein the first element is selected from the group consisting of sulfur and selenium. 
     
     
       12. The method of  claim 10 , wherein the recessing the isolation regions and the attaching the first element are separate processes, with the attaching the first element being performed after the isolation regions are recessed. 
     
     
       13. The method of  claim 10 , wherein the first element comprises sulfur or selenium, and the method further comprises attaching a second element to an additional surface of the semiconductor fin, and the second element is selected from the group consisting of antimony, arsenic, and chlorine. 
     
     
       14. The method of  claim 10  further comprising:
 forming a dummy gate stack on the semiconductor fin, wherein the first element is attached before the forming the dummy gate stack; 
 forming an Inter-Layer Dielectric (ILD) on opposite sides of the dummy gate stack; and 
 removing the dummy gate stack to form a recess in the ILD. 
 
     
     
       15. The method of  claim 10  further comprising:
 forming a dummy gate stack on the semiconductor fin; 
 forming an Inter-Layer Dielectric (ILD) on opposite sides of the dummy gate stack; and 
 removing the dummy gate stack to form a recess in the ILD, wherein the gate stack is formed in the recess, wherein the first element is attached through the recess. 
 
     
     
       16. A method comprising:
 forming a semiconductor fin; and 
 performing a passivation process on a top surface and sidewalls of the semiconductor fin using species comprising a first element, a second element, and a third element, wherein the first element, the second element, and the third element are different from each other, and wherein:
 the first element is selected from the group consisting essentially of sulfur, selenium, and combinations thereof; 
 the second element is selected from the group consisting essentially of antimony, sulfur, arsenic, and combinations thereof; and 
 the third element is selected from the group consisting essentially of arsenic, chlorine, and combinations thereof. 
 
 
     
     
       17. The method of  claim 10 , wherein the first element comprises sulfur. 
     
     
       18. The method of  claim 16 , wherein the semiconductor fin comprises a (100) surface, a (110) surface, and a (111) surface, wherein the first element is attached to the (100) surface to terminate dangling bonds, the second element is attached to the (110) surface to terminate dangling bonds, and the third element is attached to the (111) surface to terminate dangling bonds. 
     
     
       19. The method of  claim 16  further comprising forming a gate stack on the semiconductor fin. 
     
     
       20. The method of  claim 16 , wherein the passivation process is performed at an elevated temperature in a range between about 100° C. and about 500° C.