Semiconductor-on-insulator wafer having a composite insulator layer

Abstract

Various embodiments of the present disclosure are directed towards a semiconductor wafer. The semiconductor wafer comprises a handle wafer. A first oxide layer is disposed over the handle wafer. A device layer is disposed over the first oxide layer. A second oxide layer is disposed between the first oxide layer and the device layer, wherein the first oxide layer has a first etch rate for an etch process and the second oxide layer has a second etch rate for the etch process, and wherein the second etch rate is greater than the first etch rate.

What is claimed is: 
     
       1. A method for forming a semiconductor wafer, the method comprising:
 forming a first oxide layer on a handle wafer via a thermal oxidation process; 
 forming an etch stop layer over a donor wafer; 
 forming a device layer over the etch stop layer; 
 forming a second oxide layer on the device layer via a chemical vapor deposition (CVD) process; 
 bonding the first oxide layer to the second oxide layer, wherein both the first oxide layer and the second oxide layer are disposed between the device layer and the handle wafer; and 
 after the first oxide layer is bonded to the second oxide layer, removing the donor wafer via a first etching process. 
 
     
     
       2. The method of  claim 1 , further comprising:
 after the first oxide layer is bonded to the second oxide layer, removing the etch stop layer via a second etching process. 
 
     
     
       3. The method of  claim 2 , wherein:
 the etch stop layer is formed via an epitaxy process. 
 
     
     
       4. The method of  claim 1 , further comprising:
 before the etch stop layer is formed over the donor wafer, forming a processing layer over the donor wafer, wherein the etch stop layer is formed over the processing layer. 
 
     
     
       5. The method of  claim 4 , wherein:
 the processing layer is formed by a first epitaxy process; 
 the etch stop layer is formed by a second epitaxy process; and 
 the device layer is formed by a third epitaxy process. 
 
     
     
       6. The method of  claim 1 , further comprising:
 before the first oxide layer is bonded to the second oxide layer, removing edge regions of the second oxide layer, edge regions of the device layer, and edge regions of the etch stop layer, wherein when the first oxide layer is bonded to the second oxide layer, outermost sidewalls of the second oxide layer, outermost sidewalls of the device layer, and outermost sidewalls of the etch stop layer are disposed between outermost sidewalls of the first oxide layer. 
 
     
     
       7. The method of  claim 1 , wherein:
 the first oxide layer has a first dielectric strength; and 
 the second oxide layer has a second dielectric strength that is less than the first dielectric strength. 
 
     
     
       8. The method of  claim 1 , wherein:
 the first oxide layer has a first density; and 
 the second oxide layer has a second density different than the first density. 
 
     
     
       9. The method of  claim 8 , wherein the second density is less than the first density. 
     
     
       10. The method of  claim 8 , wherein the second density is greater than the first density. 
     
     
       11. The method of  claim 1 , wherein:
 the first oxide layer has a first thickness; 
 the second oxide layer has a second thickness; and 
 a sum of the first thickness and the second thickness is less than or equal to about 2 micrometers (um). 
 
     
     
       12. The method of  claim 11 , wherein a ratio of the second thickness to the first thickness is between about 0.1 and about 10. 
     
     
       13. The method of  claim 11 , wherein the second thickness is between about 100 angstroms (Å) and about 1 um. 
     
     
       14. A method for forming a semiconductor-on-insulator (SOI) wafer, the method comprising:
 growing a first insulator layer on a first semiconductor wafer via an oxidation process; 
 forming an etch stop layer over a second semiconductor wafer; 
 forming a semiconductor layer over the etch stop layer and the second semiconductor wafer; 
 depositing a second insulator layer over the semiconductor layer and the etch stop layer via a deposition process; 
 bonding the first insulator layer to the second insulator layer, such that the first insulator layer, the second insulator layer, and the semiconductor layer are disposed between the first semiconductor wafer and the second semiconductor wafer; and 
 after the first insulator layer is bonded to the second insulator layer, removing the second semiconductor wafer and the etch stop layer to expose the semiconductor layer. 
 
     
     
       15. The method of  claim 14 , wherein the first insulator layer is grown on an upper surface of the first semiconductor wafer, a bottom surface of the first semiconductor wafer, and opposite sidewalls of the first semiconductor wafer. 
     
     
       16. The method of  claim 14 , wherein the oxidation process comprises heating the first semiconductor wafer to about 1000° C. 
     
     
       17. The method of  claim 16 , wherein the deposition process comprises heating the second semiconductor wafer to a processing temperature that is less than about 800° C. 
     
     
       18. A method for forming a semiconductor-on-insulator (SOI) wafer, the method comprising:
 growing a first insulator layer on a handle wafer via an oxidation process; 
 growing a processing layer on a donor wafer via a first epitaxial process; 
 growing an etch stop layer on the processing layer via a second epitaxial process; 
 growing a device layer on the etch stop layer via a third epitaxial process; 
 depositing a second insulator layer over the device layer, the processing layer, and the etch stop layer via a chemical vapor deposition (CVD) process; 
 removing edge regions of the second insulator layer, the etch stop layer, the processing layer, and the device layer; 
 after the edge regions of the second insulator layer, the etch stop layer, the processing layer, and the device layer are removed, bonding the second insulator layer to the first insulator layer, such that outermost sidewalls of the second insulator layer, outermost sidewalls of the etch stop layer, outermost sidewalls of the processing layer, and outermost sidewalls of the device layer are disposed between outermost sidewalls of the first insulator layer; and 
 after the second insulator layer is bonded to the first insulator layer, removing the donor wafer, the processing layer, and the etch stop layer to expose the device layer. 
 
     
     
       19. The method of  claim 18 , wherein:
 the oxidation process comprises heating the handle wafer to about 1000° C.; and 
 the CVD process comprises heating the donor wafer to a processing temperature that is less than about 200° C. 
 
     
     
       20. The method of  claim 18 , wherein:
 the first insulator layer comprises oxygen; and 
 the second insulator layer comprises oxygen.