Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a gate stack, a first doped region, a second doped region, and a buried doped region. The first doped region has a first conductivity type and is located in the substrate at a first side of the gate stack. The second doped region has the first conductivity type and is located in the substrate at a second side of the gate stack. The buried doped region has the first conductivity type and is buried in the substrate, extended from the first doped region to the second doped region, and separated from the gate stack by a distance.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a gate stack, disposed on a substrate, the gate stack comprises a gate dielectric layer and a gate electrode on the gate dielectric layer; 
 a first doped region having a first conductivity type, located in the substrate at a first side of the gate stack; 
 a second doped region having the first conductivity type, located in the substrate at a second side of the gate stack, wherein the first doped region and second doped region are not covered by the gate dielectric layer; 
 a first lightly doped region having the first conductivity type, located in the substrate between the gate stack and the first doped region; 
 a second lightly doped region having the first conductivity type, located in the substrate between the gate stack and the second doped region; and 
 a buried doped region having the first conductivity type, buried in the substrate below the first lightly doped region and the second lightly doped region, extended from the first doped region to the second doped region, and separated from the gate stack by a distance, 
 wherein the first conductivity type is n-type, and the buried doped region is in physical contact with the first doped region and the second doped region, 
 wherein the buried doped region is separated from the first lightly doped region and the second lightly doped region by p-type doped regions therebetween. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein a doping concentration of the buried doped region is lower than a doping concentration of the first doped region or a doping concentration of the second doped region. 
     
     
       3. The semiconductor device according to  claim 1 , further comprising:
 spacers disposed on the substrate to cover sidewalls of the gate electrode and the gate dielectric layer, wherein outer sidewalls of the spacers are aligned with sidewalls of the first doped region and the second doped region in a direction perpendicular to a top surface of the substrate. 
 
     
     
       4. The semiconductor device according to  claim 1 , wherein the gate electrode is a second conductivity type, and the second conductivity type is p-type which is opposite to the first conductivity type. 
     
     
       5. The semiconductor device according to  claim 1 , wherein the substrate has a second conductivity type, and the second conductivity type is p-type that is opposite to the first conductivity type. 
     
     
       6. The semiconductor device according to  claim 1 , wherein the substrate comprises a well having a second conductivity type, the second conductivity type is p-type that is opposite to the first conductivity type, and the first doped region, the second doped region, and the buried doped region are in the well, wherein the p-type doped regions are portions of the well. 
     
     
       7. The semiconductor device according to  claim 1 , wherein a bottom surface of the buried doped region is coplanar with bottom surfaces of the first doped region and the second doped region. 
     
     
       8. A semiconductor device, comprising:
 a substrate; 
 a gate stack, disposed on the substrate, the gate stack comprises a gate dielectric layer and a gate electrode on the gate dielectric layer; 
 a first doped region and a second doped region located in the substrate and beside the gate stack, wherein the first doped region and second doped region are not covered by the gate dielectric layer; 
 a surface channel, between the first doped region and the second doped region and under the gate stack; and 
 a buried channel which is a buried doped region, extending from the first doped region to the second doped region and under the surface channel, 
 a first lightly doped region, adjacent to the first doped region and between the gate stack and the buried doped region; 
 a second lightly doped region, adjacent to the second doped region and between the gate stack and the buried doped region, 
 wherein the buried channel, the first doped region, the second doped region, the first lightly doped region, and the second lightly doped region have a first conductivity type and are located in a well of the substrate, 
 wherein the buried channel is in physical contact with the first doped region and the second doped region, and separated from the first lightly doped region and the second lightly doped region by portions of the well therebetween, and the well and the gate electrode have a second conductivity type opposite to the first conductivity type. 
 
     
     
       9. The semiconductor device of  claim 8 , further comprising a spacer disposed on the substrate and covering sidewalls of the gate dielectric layer and a gate electrode of the gate stack, wherein an outer sidewall of the spacer is aligned with a sidewall of the first doped region contacting the first lightly doped region. 
     
     
       10. The semiconductor device of  claim 8 , wherein the buried doped region has a thickness ranging from 5 nm to 10 nm. 
     
     
       11. The semiconductor device of  claim 8 , wherein the buried doped region is separated from the gate dielectric layer of the gate stack, and a vertical distance between buried doped region and the gate dielectric layer ranges from 50 nm to 60 nm. 
     
     
       12. The semiconductor device of  claim 8 , wherein the first conductivity type is n-type, and the second conductivity type is p-type. 
     
     
       13. The semiconductor device of  claim 8 , wherein the first conductivity type is p-type, and the second conductivity type is n-type. 
     
     
       14. The semiconductor device of  claim 8 , wherein a vertical distance between a top surface of the buried doped region and a bottom surface of the gate dielectric layer is greater than a thickness of the buried doped region defined by a vertical distance between the top surface of the buried doped region and a bottom surface of the buried doped region. 
     
     
       15. A method of manufacturing a semiconductor device, comprising:
 providing a substrate; 
 performing a first implantation process to form a buried doped region in the substrate, wherein the buried doped region is away from a top surface of the substrate; 
 forming a gate stack on the substrate, the gate stack comprises a gate dielectric layer and a gate electrode on the gate dielectric layer; 
 forming spacers on sidewalls of the gate electrode and the gate dielectric layer; and 
 performing a second implantation process to form a first doped region and a second doped region in the substrate and beside the gate stack, wherein the second implantation process is performed after forming the spacers, and sidewalls of the first doped region and the second doped region are formed to be aligned with outer sidewalls of the spacers in a direction perpendicular to a top surface of the substrate, 
 wherein the first doped region and the second doped region are laterally aside the buried doped region, and the first doped region and second doped region are not covered by the gate dielectric layer. 
 
     
     
       16. The method of  claim 15 , wherein the first implantation process is performed using a first energy value which is less than or the same as a second energy value of the second implantation process. 
     
     
       17. The method of  claim 15 , wherein a bottom surface of the buried doped region is formed to be coplanar with bottom surfaces of the first doped region and the second doped region. 
     
     
       18. The method of  claim 15 , wherein after the gate stack is formed and before the spacers are formed, further comprising:
 performing a third implantation process to form a first lightly doped region and a second lightly doped region in the substrate beside the gate stack. 
 
     
     
       19. The method of  claim 18 , wherein performing the first implantation process, the second implantation process, and the third implantation process comprise implanting n-type dopants in the substrate. 
     
     
       20. The method of  claim 19 , wherein the gate electrode is doped with a p-type dopant.