US11011431B2ActiveUtilityA1
Semiconductor structure and manufacturing method thereof
Assignee: TAIWAN SEMICONDUCTOR MFG CO LTDPriority: Sep 18, 2017Filed: Sep 12, 2020Granted: May 18, 2021
Est. expirySep 18, 2037(~11.2 yrs left)· nominal 20-yr term from priority
H10W 99/00H10W 90/736H10W 90/724H10W 90/722H10W 90/297H10W 90/288H10W 90/28H10W 76/17H10W 76/12H10W 74/15H10W 72/07354H10W 72/07254H10W 72/07236H10W 72/01225H10W 72/01223H10W 72/877H10W 72/354H10W 72/347H10W 72/252H10W 72/247H10W 72/244H10W 72/073H10W 72/072H10W 42/271H10W 42/121H10W 42/20H10W 90/701H10W 90/00H10W 76/60H10W 74/141H10W 74/01H10W 72/90H10W 70/635H10W 40/251H10W 40/22H10D 84/0151H10D 84/038H01L 23/562H01L 2224/83104H01L 24/92H01L 2224/2919H01L 2225/06568H01L 24/32H01L 2224/73253H01L 2224/83102H01L 24/16H01L 2225/06589H01L 2224/16235H01L 2924/014H01L 2924/3512H01L 2224/92242H01L 2224/73204H01L 2224/1132H01L 24/11H01L 2924/0665H01L 2225/06537H01L 23/10H01L 21/823481H01L 23/3185H01L 2225/06541H01L 24/13H01L 2224/9202H01L 2225/06513H01L 2224/16227H01L 21/56H01L 2224/81815H01L 23/49816H01L 23/49827H01L 2224/16145H01L 2224/92222H01L 2224/13111H01L 2924/3025H01L 24/02H01L 2224/92225H01L 23/552H01L 24/17H01L 2224/33181H01L 2924/16724H01L 25/50H01L 24/29H01L 2224/32245H01L 25/0657H01L 23/04H01L 24/81H01L 2224/16146H01L 2224/13024H01L 2224/11334H01L 2924/00014H01L 2224/11H01L 24/33H01L 2924/15311H01L 24/83H01L 2224/17181H01L 2224/131H01L 2224/13116H01L 2924/16747
69
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Cited by
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References
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Claims
Abstract
A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a sidewall substantially orthogonal to the first surface and the second surface; and a metallic layer surrounding and connected with the sidewall of the substrate, wherein the metallic layer includes an exposed surface substantially level with the first or second surface of the substrate. Further, a method of manufacturing the semiconductor structure is also disclosed.
Claims
exact text as granted — not AI-modifiedThe invention claimed is:
1. A semiconductor structure, comprising:
a substrate including a first surface, a second surface opposite to the first surface, a sidewall substantially orthogonal to the first surface and the second surface; and
a metallic layer surrounding and connected with the sidewall of the substrate;
a die disposed over the second surface of the substrate; and
a conductive bump disposed at the first surface of the substrate,
wherein the metallic layer includes an exposed surface substantially level with the first surface of the substrate.
2. The semiconductor structure of claim 1 , wherein the metallic layer entirely covers the sidewall of the substrate.
3. The semiconductor structure of claim 1 , wherein the metallic layer is disposed conformal to the sidewall of the substrate.
4. The semiconductor structure of claim 1 , wherein the metallic layer includes a second sidewall substantially orthogonal to the exposed surface and substantially parallel to the sidewall of the substrate.
5. The semiconductor structure of claim 1 , wherein the metallic layer covers a corner of the substrate.
6. The semiconductor structure of claim 1 , further comprising a second conductive bump disposed between the substrate and the die.
7. The semiconductor structure of claim 1 , further comprising a heat dissipation member disposed over the die, the substrate and the metallic layer.
8. The semiconductor structure of claim 7 , wherein the heat dissipation member is disposed over at least a portion of the second surface of the substrate and at least a portion of the exposed surface of the metallic layer.
9. The semiconductor structure of claim 8 , wherein the heat dissipation member is attached to the metallic layer by an adhesive.
10. The semiconductor structure of claim 1 , wherein the metallic layer includes aluminum, copper, nickel, gold or silver.
11. A semiconductor structure, comprising:
a substrate including a first sidewall;
a first polymeric layer disposed over the substrate and including a second sidewall coupled and aligned with the first sidewall;
a second polymeric layer disposed below the substrate and including a third sidewall coupled and aligned with the first sidewall; and
a metallic layer surrounding and connected with the first sidewall, the second sidewall and the third sidewall.
12. The semiconductor structure of claim 11 , wherein the first polymeric layer is separated from the second polymeric layer.
13. The semiconductor structure of claim 11 , further comprising:
a die disposed over the first polymeric layer;
a first conductive bump disposed at the second polymeric layer;
a second conductive bump disposed between the die and the first polymeric layer.
14. The semiconductor structure of claim 11 , wherein the metallic layer entirely covers the first sidewall, the second sidewall and the third sidewall.
15. The semiconductor structure of claim 11 , wherein the metallic layer includes an exposed surface substantially level with a surface of the second polymeric layer.
16. The semiconductor structure of claim 11 , wherein the metallic layer is substantially orthogonal to the substrate, the first polymeric layer and the second polymeric layer.
17. A method of manufacturing a semiconductor structure, comprising:
providing a substrate including a first surface, a second surface opposite to the first surface, a sidewall substantially orthogonal to the first surface and the second surface;
disposing a metallic layer surrounding and connected with the sidewall of the substrate;
disposing a die over the second surface of the substrate; and
disposing a conductive bump at the first surface of the substrate,
wherein the disposing of the metallic layer includes forming an exposed surface substantially level with the first surface of the substrate.
18. The method of claim 17 , wherein the metallic layer is disposed by coating, rolling or sticking.
19. The method of claim 17 , further comprising disposing a polymeric layer over the second surface of the substrate, wherein the disposing of the metallic layer is performed after the disposing of the polymeric layer.
20. The method of claim 17 , wherein the sidewall of the substrate is formed by singulation operations.Cited by (0)
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