Logic drive based on standard commodity FPGA IC chips

Abstract

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

What is claimed is: 
     
       1. A chip package comprising:
 a first semiconductor chip; 
 a conductive via in a space beyond and extending from, in a horizontal direction, a sidewall of the first semiconductor chip, wherein the conductive via provides connection in a vertical direction perpendicular to the horizontal direction; 
 a polymer layer in the space, wherein the polymer layer contacts the conductive via and the sidewall of the first semiconductor chip and has a portion between the conductive via and the sidewall of the first semiconductor chip, wherein the conductive via vertically extends through the polymer layer; 
 a first interconnection scheme over the first semiconductor chip, the polymer layer and the conductive via and across the sidewall of the first semiconductor chip, wherein the first interconnection scheme comprises a first interconnection metal layer over the first semiconductor chip, the polymer layer and the conductive via, a second interconnection metal layer over the first interconnection metal layer and a first insulating dielectric layer between the first and second interconnection metal layers, wherein the first interconnection scheme comprises a metal interconnect across over the sidewall of the first semiconductor chip, wherein the first semiconductor chip couples to the conductive via through the first interconnection metal layer; and 
 a second interconnection scheme under the first semiconductor chip, the polymer layer and the conductive via and across an edge of the first semiconductor chip, wherein the second interconnection scheme comprises a first metal portion configured for power connection vertically under the first semiconductor chip, wherein the first metal portion couples to the first semiconductor chip through, in sequence, the conductive via and the first interconnection metal layer. 
 
     
     
       2. The chip package of  claim 1  further comprising a second semiconductor chip on a same plane as the first semiconductor chip, wherein the first interconnection scheme is further over the second semiconductor chip and across an edge of the second semiconductor chip, wherein the second semiconductor chip couples to the first interconnection metal layer. 
     
     
       3. The chip package of  claim 1 , wherein the first metal portion comprises a power plane provided by a third interconnection metal layer of the second interconnection scheme. 
     
     
       4. The chip package of  claim 3 , wherein the third interconnection metal layer has a thickness between 5 and 50 micrometers. 
     
     
       5. The chip package of  claim 1 , wherein the first semiconductor chip comprises a conductive interconnect coupling to the conductive via through the first interconnection metal layer, wherein a top surface of the conductive interconnect and a top surface of the polymer layer are coplanar. 
     
     
       6. The chip package of  claim 5 , wherein the conductive interconnect comprises a copper layer having a thickness between 5 and 20 micrometers. 
     
     
       7. The chip package of  claim 5 , wherein the first semiconductor chip comprises a third interconnection metal layer having a thickness between 10 nm and 3,000 nm therein and a passivation layer on the third interconnection metal layer, wherein an opening in the passivation layer is over a copper pad of the third interconnection metal layer, wherein the conductive interconnect couples to the copper pad through the opening. 
     
     
       8. The chip package of  claim 5 , wherein the top surface of the conductive interconnect, the top surface of the polymer layer and a top surface of the conductive via are coplanar. 
     
     
       9. The chip package of  claim 1 , wherein the first interconnection metal layer comprises a metal trace having a thickness between 0.5 and 5 micrometers and a width between 0.5 and 5 micrometers. 
     
     
       10. The chip package of  claim 1 , wherein the first semiconductor chip is a central-processing-unit (CPU) chip. 
     
     
       11. The chip package of  claim 1 , wherein the first semiconductor chip is a field-programmable-grate-array (FPGA) chip. 
     
     
       12. The chip package of  claim 1 , wherein the first semiconductor chip is a graphic-processing-unit (GPU) chip. 
     
     
       13. The chip package of  claim 1 , wherein the conductive via comprises a copper layer and has a height greater than 30 micrometers. 
     
     
       14. The chip package of  claim 1 , wherein the conductive via has a largest transverse dimension greater than 20 micrometers. 
     
     
       15. The chip package of  claim 1 , wherein the first interconnection metal layer comprises an adhesion layer and a copper layer on the adhesion layer. 
     
     
       16. The chip package of  claim 15 , wherein the adhesion layer comprises titanium. 
     
     
       17. The chip package of  claim 1 , wherein the second interconnection scheme further comprises a second metal portion configured for ground reference. 
     
     
       18. The chip package of  claim 17 , wherein the first and second metal portions are provided by a third interconnection metal layer of the second interconnection scheme, wherein each of the first and second metal portions has a forklike shape, wherein the first metal portion comprises a first metal stripe and second metal stripe coupling to the first metal stripe and the second metal portion comprises a third metal stripe and fourth metal stripe coupling to the third metal stripe, wherein the first, second, third and fourth metal stripes are in parallel with one another in a plane of the third interconnection metal layer, wherein the second metal stripe is between the third and fourth metal stripes and the third metal stripe is between the first and second metal stripes. 
     
     
       19. The chip package of  claim 1 , wherein the second interconnection scheme comprises a third interconnection metal layer under the first semiconductor chip, polymer layer and conductive via and across the edge of the first semiconductor chip and a second insulating dielectric layer on the third interconnection metal layer, wherein an opening in the second insulating dielectric layer is over a contact point of the third interconnection metal layer, wherein the conductive via is on the contact point and the polymer layer is on the second insulating dielectric layer, wherein the first metal portion couples to the first semiconductor chip through, in sequence, the contact point, conductive via and first interconnection metal layer. 
     
     
       20. The chip package of  claim 1 , wherein a top surface of the conductive via and a top surface of the polymer layer are coplanar. 
     
     
       21. The chip package of  claim 1 , wherein the first semiconductor chip comprises an input/output (I/O) circuit coupling to the first interconnection scheme, wherein the input/output (I/O) circuit has a driving capability between 0.1 and 2 pF. 
     
     
       22. The chip package of  claim 1 , wherein the first semiconductor chip is a memory chip. 
     
     
       23. The chip package of  claim 1 , wherein the first semiconductor chip is a static random-access-memory (SRAM) chip. 
     
     
       24. The chip package of  claim 1 , wherein the first semiconductor chip comprises a first memory cell for storing first data therein and a programmable interconnection circuit, wherein the programmable interconnection circuit comprises first and second conductive interconnects and a programmable switch circuit having a first input point coupling to the first conductive interconnect, a first output point coupling to the second conductive interconnect, and a second input point for input data for the programmable switch circuit, wherein the programmable switch circuit is configured to control, in accordance with the input data at the second input point, coupling between the first and second conductive interconnects, wherein the input data at the second input point is associated with the first data. 
     
     
       25. The chip package of  claim 24 , wherein the first semiconductor chip comprises a second memory cell for storing second data therein and a programmable selection circuit, wherein the programmable selection circuit comprises third and fourth conductive interconnects, a third input point coupling to the third conductive interconnect, a fourth input point coupling to the fourth conductive interconnect, a second output point coupling to the first conductive interconnect, and a fifth input point for input data for the programmable selection circuit, wherein the programmable selection circuit is configured to select, in accordance with the input data at the fifth input point, one of the third and fourth conductive interconnects to couple with the second output point, wherein the input data at the fifth input point is associated with the second data. 
     
     
       26. The chip package of  claim 1 , wherein the first semiconductor chip comprises a memory cell for storing a resulting value of a look-up table (LUT) for a logic operation, a selection circuit comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set, wherein the second input data set comprises input data associated with the resulting value, wherein the selection circuit is configured to select, in accordance with the first input data set, the input data from the second input data set as output data for the logic operation. 
     
     
       27. The chip package of  claim 1  further comprising a metal contact at a top surface of the chip package and vertically over the first semiconductor chip. 
     
     
       28. The chip package of  claim 27 , wherein the metal contact comprises a metal bump at the top surface of the chip package and vertically over the first semiconductor chip, wherein the metal bump comprises tin. 
     
     
       29. The chip package of  claim 1  further comprising a metal contact at a bottom surface of the chip package and vertically under the first semiconductor chip. 
     
     
       30. The chip package of  claim 29 , wherein the metal contact comprises a copper pad at the bottom surface of the chip package and vertically under the first semiconductor chip. 
     
     
       31. The chip package of  claim 1  further comprising eight first metal contacts at a top surface of the chip package and eight second metal contacts at a bottom surface of the chip package, wherein each of the eight first metal contacts is vertically aligned with one of the eight second metal contacts.