Electronic device and method of manufacturing the same

Abstract

Provided are an electronic device including a dielectric layer having an adjusted crystal orientation and a method of manufacturing the electronic device. The electronic device includes a seed layer provided on a substrate and a dielectric layer provided on the seed layer. The seed layer includes crystal grains having aligned crystal orientations. The dielectric layer includes crystal grains having crystal orientations aligned in the same direction as the crystal orientations of the seed layer.

What is claimed is: 
     
       1. An electronic device comprising:
 a substrate; 
 a seed layer on the substrate, the seed layer including crystal grains having aligned crystal orientations; 
 a dielectric layer on the seed layer, the dielectric layer including crystal grains having crystal orientations aligned in the same direction as the crystal orientations of the seed layer; and 
 an electrode on the dielectric layer. 
 
     
     
       2. The electronic device of  claim 1 , further comprising:
 a source; 
 a drain; and 
 a channel layer at an upper surface of the substrate between the source and the drain at a position corresponding to the electrode, 
 wherein the electrode is a gate electrode. 
 
     
     
       3. The electronic device of  claim 2 , wherein the channel layer comprises at least one of Si, Ge, a group III-V semiconductor, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional semiconductor material, a quantum dot, and an organic semiconductor. 
     
     
       4. The electronic device of  claim 1 , wherein the seed layer comprises at least one of an oxide, a nitride, a chalcogenide, and a two-dimensional insulator material. 
     
     
       5. The electronic device of  claim 4 , wherein the oxide comprises at least one oxide of Y, Si, Al, Hf, Zr, La, Mo, W, Ru, and Nb. 
     
     
       6. The electronic device of  claim 5 , wherein the oxide further comprises a dopant. 
     
     
       7. The electronic device of  claim 1 , wherein the seed layer has a thickness of about 0.5 nm to about 3 nm. 
     
     
       8. The electronic device of  claim 1 , wherein the dielectric layer comprises a ferroelectric. 
     
     
       9. The electronic device of  claim 1 , wherein the dielectric layer comprises at least one oxide of Hf, Si, Al, Zr, Y, La, Gd, and Sr. 
     
     
       10. The electronic device of  claim 9 , wherein the dielectric layer further comprises a dopant. 
     
     
       11. The electronic device of  claim 1 , wherein the dielectric layer has a thickness of about 0.5 nm to about 20 nm. 
     
     
       12. The electronic device of  claim 1 , wherein the crystal orientations of the crystal grains of the seed layer and of the dielectric layer have a <111> orientation. 
     
     
       13. The electronic device of  claim 1  wherein:
 the electrode is a first electrode, and 
 the substrate is a second electrode. 
 
     
     
       14. A method of manufacturing an electronic device, the method comprising:
 preparing a substrate having a channel layer therein; 
 forming a seed layer on the channel layer, the seed layer comprising crystal grains having aligned crystal orientations; 
 forming a dielectric layer on the seed layer, the dielectric layer comprising crystal grains having crystal orientations aligned in the same direction as the crystal orientations of the seed layer; and 
 forming a gate electrode on the dielectric layer. 
 
     
     
       15. The method of  claim 14 , wherein the forming of the seed layer includes
 depositing an amorphous dielectric material layer on the channel layer, and 
 crystallizing the deposited amorphous dielectric material layer. 
 
     
     
       16. The method of  claim 14 , wherein the forming of the seed layer, includes transferring crystal grains having aligned crystal orientations onto the channel layer. 
     
     
       17. The method of  claim 14 , wherein the forming of the dielectric layer includes
 depositing an amorphous dielectric material layer on the seed layer, and 
 crystallizing the amorphous dielectric material layer. 
 
     
     
       18. The method of  claim 14 , wherein the dielectric layer comprises a ferroelectric. 
     
     
       19. The method of  claim 14 , wherein the dielectric layer comprises at least one oxide of Hf, Si, Al, Zr, Y, La, Gd, and Sr. 
     
     
       20. The method of  claim 19 , wherein the dielectric layer further comprises a dopant. 
     
     
       21. The electronic device of  claim 13 , wherein the electronic device is a capacitor. 
     
     
       22. The electronic device of  claim 21 , wherein the dielectric layer has a remnant polarization. 
     
     
       23. A memory device comprising:
 a transistor; and 
 the electronic device of  claim 21  electrically connected to a source region of the transistor. 
 
     
     
       24. The electronic device of  claim 1 , further comprising:
 an amorphous dielectric layer between the seed layer and the substrate. 
 
     
     
       25. The electronic device of  claim 1 , further comprising:
 a crystalline dielectric layer having a crystal orientation different from the aligned crystal orientations of the seed layer between the seed layer and the substrate.