Gate structure with barrier layer and method for forming the same

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer over a substrate. A first metal layer is formed in the first insulating layer and over the substrate. A silicon- and fluorine-containing barrier layer is formed between the first insulating layer and the first metal layer and between the substrate and the first metal layer. The silicon- and fluorine-containing barrier layer has a silicon content in a range from about 5% to about 20%.

What is claimed is: 
     
       1. A semiconductor device structure, comprising:
 a first insulating layer over a substrate; 
 a first metal layer formed in the first insulating layer and over the substrate; 
 a silicon- and fluorine-containing barrier layer formed between the first insulating layer and the first metal layer and between the substrate and the first metal layer; 
 a second metal layer formed between the first insulating layer and the silicon- and fluorine-containing barrier layer and in direct contact with the silicon- and fluorine-containing barrier layer, wherein the second metal layer is an N-type work function metal layer; 
 a metal nitride layer formed between the first insulating layer and the second metal layer; and 
 a metal oxide layer sandwiched between the substrate and the metal nitride layer, 
 wherein the silicon- and fluorine-containing barrier layer has a silicon content in a range from about 5% to about 20%, wherein the silicon- and fluorine-containing barrier layer is a metal layer with silicon dopants and fluorine dopants, and wherein the silicon- and fluorine-containing barrier layer has a thickness in a range from about 20 Å to about 50 Å, and 
 wherein the metal nitride layer is in direct contact with the metal oxide layer, and the silicon- and fluorine-containing barrier layer is in direct contact with the second metal layer. 
 
     
     
       2. The semiconductor device structure as claimed in  claim 1 , wherein the second metal layer is formed between the substrate and the silicon- and fluorine-containing barrier layer. 
     
     
       3. The semiconductor device structure as claimed in  claim 2 , wherein the second metal layer is made of TiAlN or TaCN. 
     
     
       4. The semiconductor device structure as claimed in  claim 2 , wherein the metal nitride layer is made of WN or TaN. 
     
     
       5. The semiconductor device structure as claimed in  claim 1 , wherein the first metal layer is a metal bulk layer. 
     
     
       6. The semiconductor device structure as claimed in  claim 5 , wherein the silicon- and fluorine-containing barrier layer and the metal bulk layer comprise tungsten. 
     
     
       7. The semiconductor device structure as claimed in  claim 1 , wherein the silicon- and fluorine-containing barrier layer comprises silicon-fluorine bonds formed therein. 
     
     
       8. The semiconductor device structure as claimed in  claim 1 , wherein the first metal layer has a thickness in a range from about 1400 Å to about 2000 Å. 
     
     
       9. The semiconductor device structure as claimed in  claim 1 , further comprising:
 a fin structure protruding from a substrate; and 
 a source/drain feature formed over the fin structure; 
 wherein a bottom surface of the metal oxide layer vertically over the isolation feature is lower than a top surface of the source/drain feature and is higher than a bottom surface of the source/drain feature. 
 
     
     
       10. A semiconductor device structure, comprising:
 a fin structure protruding from a substrate; and 
 a gate structure formed over the substrate, comprising:
 a gate insulating layer over the fin structure, wherein the gate insulating layer is made of metal oxide; 
 a metal nitride layer over and in direct contact with the gate insulating layer; 
 a work function metal layer over and in direct contact with the metal nitride layer, wherein the work function metal layer is an N-type work function metal layer; 
 a silicon-containing metal nucleation layer over and in direct contact with the work function metal layer; and 
 a metal bulk layer over the silicon-containing metal nucleation layer, 
 
 wherein the metal bulk layer and the silicon-containing metal nucleation layer are made of the same metal material, wherein the silicon-containing metal nucleation layer is a metal layer with silicon dopants and fluorine dopants and has a silicon content in a range from about 5% to about 20%, and wherein the silicon-containing metal nucleation layer has a thickness in a range from about 20 Å to about 50 Å, and 
 wherein the work function metal layer is sandwiched between the metal nitride layer and the silicon-containing metal nucleation layer. 
 
     
     
       11. The semiconductor device structure as claimed in  claim 10 , wherein the metal material comprises tungsten. 
     
     
       12. The semiconductor device structure as claimed in  claim 10 , wherein the work function metal layer is made of TiAlN or TaCN. 
     
     
       13. The semiconductor device structure as claimed in  claim 10 , further comprising:
 a gate spacer layer formed on a sidewall of the gate structure; and 
 an insulating layer formed around the gate spacer layer, 
 wherein the gate spacer layer is in direct contact with the gate insulating layer and the insulating layer. 
 
     
     
       14. A method of forming a semiconductor device structure, comprising:
 forming a fin structure protruding from a substrate; 
 forming a first insulating layer over the substrate and having an opening that exposes the fin structure; 
 forming a metal nitride layer to conformally cover an inner surface of the opening; 
 forming a work function metal layer to conformally cover the metal nitride layer in the opening, wherein the work function metal layer is an N-type work function metal layer; 
 forming a silicon-containing metal nucleation layer with silicon dopants to conformally cover an exposed top surface of the work function metal layer; and 
 forming a metal bulk layer over the silicon-containing metal nucleation layer and filling the opening using a fluorine-containing gas, so that fluorine ions generated by the formation of the metal bulk layer diffuse into the silicon-containing metal nucleation layer to form fluorine dopants in the silicon-containing metal nucleation layer, 
 wherein the silicon-containing metal nucleation layer is a metal layer with silicon-fluorine bonds generated by the silicon dopants and fluorine dopants formed therein and has a silicon content in a range from about 5% to about 20%, and wherein the silicon-containing metal nucleation layer has a thickness in a range from about 20 Å to about 50 Å, and 
 wherein the silicon-containing metal nucleation layer is formed by an atomic layer deposition process, and the atomic layer deposition process comprises using a metal-containing gas, a silicon-containing gas, a reducing gas, and an inert gas, and the metal-containing gas comprises WF 6 , the silicon-containing gas comprises SiCl 2 H 2 , the inert gas comprises Ar, and the reducing gas comprises borane or H 2 . 
 
     
     
       15. The method as claimed in  claim 14 , wherein the metal bulk layer is formed by a chemical vapor deposition process. 
     
     
       16. The method as claimed in  claim 14 , further comprising forming a second insulating layer to conformally cover the inner surface of the opening prior to the formation of the work function metal layer. 
     
     
       17. The method as claimed in  claim 14 , further comprising:
 forming a first masking layer over the substrate; 
 forming a second masking layer over the first masking layer; 
 forming a patterned third masking layer over the second masking layer; 
 patterning the second masking layer and the first masking layer through the patterned third masking layer to expose portions of the substrate; 
 removing the patterned third masking layer; and 
 etching the substrate exposed by the second masking layer and the first masking layer to form the fin structure. 
 
     
     
       18. The method as claimed in  claim 17 , further comprising:
 forming an insulating layer covering the first masking layer, the second masking layer, and the fin structure; 
 polishing the insulating layer to expose the second masking layer; 
 removing the second masking layer and the first masking layer; and 
 removing upper portions of the insulating layer to form an isolation feature around the fin structure. 
 
     
     
       19. The method as claimed in  claim 14 , wherein the work function metal layer is made of TiAlN or TaCN. 
     
     
       20. The method as claimed in  claim 19 , wherein the metal nitride layer is made of WN or TaN.