Semiconductor package and fabrication method thereof

Abstract

A semiconductor package includes a substrate having thereon a high-frequency chip and a circuit component susceptible to high-frequency signal interference; a ground pad on the and between the high-frequency chip and the circuit component; a metal-post reinforced glue wall on the ground pad; a molding compound surrounding the metal-post reinforced glue wall and surrounding the high-frequency chip and the circuit component; and a conductive layer disposed on the molding compound and in contact with the metal-post reinforced glue wall. The metal-post reinforced glue wall comprises first metal posts and glue attached to the first metal posts. An interface between a base of each of the first metal posts and the ground pad has a root mean square (RMS) roughness that is less than 1.0 micrometer.

What is claimed is: 
     
       1. A semiconductor package, comprising:
 a substrate having a high-frequency chip and a circuit component susceptible to high-frequency signal interference on a top surface of the substrate; 
 a ground pad disposed on the top surface of the substrate and between the high-frequency chip and the circuit component; 
 a metal-post reinforced glue wall disposed on the ground pad, wherein the metal-post reinforced glue wall comprises a plurality of first metal posts, wherein one end of each of the plurality of first metal posts is fixed on the ground pad, and the other end is suspended, wherein the metal-post reinforced glue wall further comprises a glue attached to a surface of each of the plurality of the first metal posts, and wherein an interface between a base of each of the first metal posts and the ground pad has a root mean square (RMS) roughness that is less than 1.0 micrometer; 
 a molding compound surrounding the metal-post reinforced glue wall and surrounding the high-frequency chip and the circuit component; and 
 a conductive layer disposed on the molding compound and in contact with the metal-post reinforced glue wall. 
 
     
     
       2. The semiconductor package according to  claim 1 , wherein the RMS roughness of the interface between the base of each of the plurality of first metal posts and the ground pad is less than or equal to 0.4 micrometers. 
     
     
       3. The semiconductor package according to  claim 1 , wherein an interface between a top surface of the each of the plurality of first metal posts and the conductive layer has a RMS roughness that is less than 1.0 micrometer. 
     
     
       4. The semiconductor package according to  claim 3 , wherein the RMS roughness of the interface between the base of each of the plurality of first metal posts and the ground pad is less than or equal to 0.4 micrometers. 
     
     
       5. The semiconductor package according to  claim 1 , wherein the metal-post reinforced glue wall comprises a plurality of second metal posts on the ground pad, wherein the plurality of first metal posts and the plurality of second metal posts are arranged in a staggered manner. 
     
     
       6. The semiconductor package according to  claim 5 , wherein the conductive layer comprises an antenna pattern electrically coupled to one of the second metal posts. 
     
     
       7. The semiconductor package according to  claim 6 , wherein the antenna pattern is electrically coupled to one of the plurality of second metal posts through a lead wire on the molding compound. 
     
     
       8. The semiconductor package according to  claim 7  further comprising:
 a ground mesh on the molding compound to isolate the antenna pattern. 
 
     
     
       9. The semiconductor package according to  claim 8 , wherein the antenna pattern, the lead wire, and the ground mesh are embedded into the molding compound. 
     
     
       10. The semiconductor package according to  claim 6 , wherein the conductive layer further comprises an electromagnetic interference (EMI) shielding pattern electrically coupled to the plurality of first metal posts. 
     
     
       11. The semiconductor package according to  claim 10 , wherein the EMI shielding pattern is not coplanar with the antenna pattern. 
     
     
       12. The semiconductor package according to  claim 6 , wherein the glue is non-conductive glue. 
     
     
       13. The semiconductor package according to  claim 5 , wherein the glue is also attached to a surface of each of the plurality of the second metal posts. 
     
     
       14. The semiconductor package according to  claim 1 , wherein the glue comprises a thermosetting resin, a thermoplastic resin or an ultraviolet (UV) curing resin. 
     
     
       15. The semiconductor package according to  claim 1 , wherein the glue comprises a conductive paste. 
     
     
       16. The semiconductor package according to  claim 1 , wherein the glue comprises conductive particles. 
     
     
       17. The semiconductor package according to  claim 16 , wherein the conductive particles comprise copper, silver, gold, aluminum, nickel, palladium, any combination or alloy thereof, or graphene. 
     
     
       18. The semiconductor package according to  claim 1 , wherein a composition of the molding compound is different from a composition of the glue. 
     
     
       19. The semiconductor package according to  claim 1 , wherein a top surface of the molding compound is flush with a top surface of the metal-post reinforced glue wall. 
     
     
       20. The semiconductor package according to  claim 1 , wherein the metal-post reinforced glue wall comprises a mold-flow channel that allows the molding compound to flow therethrough. 
     
     
       21. A semiconductor package, comprising:
 a substrate having a high-frequency chip and a circuit component susceptible to high-frequency signal interference on a top surface of the substrate; 
 a ground ring disposed on the top surface of the substrate and at least around the circuit component; 
 a metal-post reinforced glue wall disposed on the ground ring, wherein the metal-post reinforced glue wall comprises a plurality of first metal posts, wherein one end of each of the plurality of first metal posts is fixed on the ground ring, and the other end is suspended, wherein the metal-post reinforced glue wall further comprises a glue attached to a surface of each of the plurality of the first metal posts; 
 a molding compound surrounding the metal-post reinforced glue wall and surrounding the high-frequency chip and the circuit component; 
 a conductive layer disposed on the molding compound and in contact with the metal-post reinforced glue wall; 
 a passivation layer at least partially covering the conductive layer; and 
 a plurality of antenna patterns disposed on the passivation layer. 
 
     
     
       22. The semiconductor package according to  claim 21 , wherein the conductive layer overlaps with the high-frequency chip and the circuit component. 
     
     
       23. The semiconductor package according to  claim 22 , wherein the high-frequency chip is shielded from the circuit component by the metal-post reinforced glue wall and the conductive layer. 
     
     
       24. The semiconductor package according to  claim 21 , wherein the plurality of antenna patterns are electrically connected to respective signal pads on the substrate through a plurality of second metal posts disposed adjacent to the metal-post reinforced glue wall. 
     
     
       25. The semiconductor package according to  claim 24 , wherein the signal pads are electrically connected to the high-frequency chip through a plurality of traces in the substrate. 
     
     
       26. The semiconductor package according to  claim 21 , wherein an interface between a base of each of the first metal posts and the ground pad has a root mean square (RMS) roughness that is less than 1.0 micrometer. 
     
     
       27. A semiconductor package, comprising:
 a substrate having a high-frequency chip and a circuit component susceptible to high-frequency signal interference on a top surface of the substrate; 
 a ground ring disposed on the top surface of the substrate and at least around the circuit component; 
 a metal-post reinforced glue wall disposed on the ground ring, wherein the metal-post reinforced glue wall comprises a plurality of first metal posts, wherein one end of each of the plurality of first metal posts is fixed on the ground ring, and the other end is suspended, wherein the metal-post reinforced glue wall further comprises a glue attached to a surface of each of the plurality of the first metal posts; 
 a molding compound surrounding the metal-post reinforced glue wall and surrounding the high-frequency chip and the circuit component; 
 a conductive layer disposed on the molding compound and in contact with the metal-post reinforced glue wall; and 
 antenna patterns being spaced apart from the conductive layer and being disposed on the molding compound along at least one side edge of the semiconductor package. 
 
     
     
       28. The semiconductor package according to  claim 27  further comprising:
 peripheral metal posts disposed in the molding compound along the at least one side edge of the semiconductor package. 
 
     
     
       29. The semiconductor package according to  claim 28 , wherein the antenna patterns are electrically connected to the peripheral metal posts through lead wires on the molding compound, respectively. 
     
     
       30. The semiconductor package according to  claim 28 , wherein the antenna patterns are electrically connected to the peripheral metal posts directly. 
     
     
       31. The semiconductor package according to  claim 30 , wherein the peripheral metal posts are bent metal posts.