Semiconductor package

Abstract

A semiconductor package according to an embodiment of the present invention Includes: a lead frame comprising a pad and a lead spaced apart from the pad by a regular interval; a semiconductor chip adhered on the pad; and a clip structure electrically connecting the semiconductor chip and the lead, wherein an one end of the clip structure connected to the semiconductor chip inclines with respect to upper surfaces of chip pads of the semiconductor chip and is adhered to the upper surfaces of the chip pads of the semiconductor chip. A semiconductor package according to another embodiment of the present invention includes: a semiconductor chip comprising one or more chip pads; one or more leads electrically connected to the chip pads; and a sealing member covering the semiconductor chip, wherein an one end of the lead inclines with respect to one surface of the chip pad and is adhered to the chip pad and an other end of the lead is exposed to the outside of the sealing member.

What is claimed is: 
     
       1. A semiconductor package comprising:
 a lead frame comprising a pad and a lead spaced apart from the pad by a regular interval; 
 a semiconductor chip adhered on the pad; and 
 a clip structure electrically connecting the semiconductor chip and the lead, 
 wherein the clip structure comprises:
 a first flat inclined part having a first end adhered to an upper surface of a chip pad provided on the semiconductor chip, the first flat inclined part being inclined with respect to the upper surface of the chip pad; 
 a first flat horizontal part extended from the first flat inclined part, the first flat horizontal part being parallel to the upper surface of the chip pad; 
 a second flat inclined part extended from the first flat horizontal part, the second flat inclined part being inclined with respect to an upper surface of the lead; and 
 a second flat horizontal part extended from the second flat inclined part and adhered to the upper surface of the lead, the second flat horizontal part being parallel to the upper surface of the lead, 
 
 wherein the first end of the first flat inclined part has an upper surface, a cut surface, and a lower surface, 
 wherein an edge formed by the lower and cut surfaces of the first end is embedded in a third adhesive layer provided on the upper surface of the chip pad. 
 
     
     
       2. The semiconductor package of  claim 1 , wherein the lead comprises a first lead and a second lead, both of which are placed at an opposite side centering around the pad, the first lead is electrically connected to a gate of the semiconductor chip, and the second lead is electrically connected to a drain of the semiconductor chip. 
     
     
       3. The semiconductor package of  claim 1 , wherein a first angle between the lower surface of the first end and the upper surface of the chip pad and a second angle between the cut surface of the first end and the upper surface of the chip pad are in the range of 10 to 85 degrees. 
     
     
       4. The semiconductor package of  claim 1 , wherein the lower surface and the cut surface of the first end incline at a regular angle in the edge and a cross-section of the edge cut along a longitudinal direction of the edge is in a V shape or a U shape. 
     
     
       5. The semiconductor package of  claim 1 , wherein the lead has a concaved part in which a first adhesive layer is filled and a lower surface of an end of the second horizontal part is adhered to the first adhesive layer. 
     
     
       6. The semiconductor package of  claim 1 , wherein the edge of the first end is in contact with the third adhesive layer along with the lower surface and the cut surface. 
     
     
       7. The semiconductor package of  claim 1 , wherein the semiconductor chip comprises a GaN semiconductor. 
     
     
       8. The semiconductor package of  claim 1 , wherein the lower surface and the cut surface of the first end incline at a regular angle in the edge and a cross-section of the edge cut along a longitudinal direction of the edge is formed to be a chamfer and contacts the upper surface of the chip pad of the semiconductor chip. 
     
     
       9. The semiconductor package of  claim 8 , wherein the edge is filled in the third adhesive layer and thus, the lower surface, the cut surface, and at least a part of the cross-section of the edge cut along a longitudinal direction of the edge simultaneously contact the third adhesive layer. 
     
     
       10. The semiconductor package of  claim 1 , wherein the pad comprises at least one or more first penetration holes and the lead comprises at least one or more of second penetration holes. 
     
     
       11. The semiconductor package of  claim 10 , wherein the lead comprises at least one or more second concaved parts interposed between the pad and the second penetration holes. 
     
     
       12. The semiconductor package of  claim 1 , wherein the third adhesive layer comprises at least one of Sn, Pb, Ag, Cu, and Au. 
     
     
       13. The semiconductor package of  claim 12 , wherein the third adhesive layer connects the first end of the first inclined part structure to the chip pad by using a soldering. 
     
     
       14. The semiconductor package of  claim 1 , wherein the lower surface and the cut surface of the first end incline at a regular angle in the edge and at least a part of a cross-section of the edge cut along a longitudinal direction of the edge contacts the upper surface of the chip pad of the semiconductor chip. 
     
     
       15. The semiconductor package of  claim 14 , wherein the edge is filled in the third adhesive layer and thus, the lower surface, the cut surface, and at least a part of the cross-section of the edge cut along a longitudinal direction of the edge simultaneously contact the third adhesive layer. 
     
     
       16. The semiconductor package of  claim 14 , wherein the cross-section formed by cutting the edge is formed to contact the upper surface of the chip pad of the semiconductor chip in a width direction with the rate of 0.3 to 0.5:1. 
     
     
       17. The semiconductor package of  claim 16 , wherein the edge is filled in the third adhesive layer and thus, the lower surface, the cut surface, and at least a part of the cross-section of the edge cut along a longitudinal direction of the edge simultaneously contact the third adhesive layer. 
     
     
       18. A semiconductor package comprising:
 a semiconductor chip comprising at least one chip pad; 
 at least one lead electrically connected to the chip pad; and 
 a sealing member covering the semiconductor chip, 
 wherein each lead comprises:
 a first flat inclined part having a first end adhered to an upper surface of a corresponding chip pad, the first flat inclined part being inclined with respect to the upper surface of the chip pad; 
 a first flat horizontal part extended from the first flat inclined part, the first flat horizontal part being parallel to the upper surface of the chip pad; 
 a second flat inclined part extended from the first flat horizontal part, the second flat inclined part being inclined with respect to a lower surface of the semiconductor chip; and 
 a second flat horizontal part extended from the second flat inclined part, the second flat horizontal part being parallel to the lower surface of the semiconductor chip, 
 
 wherein a portion of the second flat horizontal part is exposed to the outside of the sealing member, 
 wherein the first end of the first flat inclined part has an upper surface, a cut surface, and a lower surface, 
 wherein an edge formed by the lower and cut surfaces of the first end is embedded in a third adhesive layer provided on the surface of the chip pad.