Methods for forming self-aligned interconnect structures

Abstract

The present disclosure provides a method for forming interconnect structures. The method includes providing a semiconductor structure including a substrate and a conductive feature formed in a top portion of the substrate; depositing a resist layer over the substrate, wherein the resist layer has an exposure threshold; providing a radiation with an incident exposure dose to the resist layer, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer while a sum of the incident exposure dose and a reflected exposure dose from a top surface of the conductive feature is larger than the exposure threshold of the resist layer, thereby forming a latent pattern above the conductive feature; and developing the resist layer to form a patterned resist layer.

What is claimed is: 
     
       1. A method for lithography patterning, comprising:
 providing a semiconductor structure including a substrate and a conductive feature formed in a top portion of the substrate; 
 depositing a resist layer over the substrate, wherein the resist layer has an exposure threshold; 
 providing a radiation with an incident exposure dose through a photomask to the resist layer, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer while a sum of the incident exposure dose and a reflected exposure dose from a top surface of the conductive feature is larger than the exposure threshold of the resist layer, thereby forming a latent pattern above the conductive feature; and 
 developing the resist layer to form a patterned resist layer. 
 
     
     
       2. The method of  claim 1 , wherein the latent pattern is directly above the conductive feature. 
     
     
       3. The method of  claim 1 , wherein the conductive feature includes a reflective layer coated on a bulk metal. 
     
     
       4. The method of  claim 3 , wherein the reflective layer includes a first metal that is different from the bulk metal. 
     
     
       5. The method of  claim 3 , wherein the reflective layer includes a metallic alloy. 
     
     
       6. The method of  claim 3 , wherein the reflective layer includes a plurality of alternating repeating layers. 
     
     
       7. The method of  claim 1 , further comprising:
 prior to the depositing of the resist layer, forming a dielectric layer over the substrate; 
 after the developing of the resist layer, etching the dielectric layer using the patterned resist layer as an etch mask, thereby forming an opening exposing the top surface of the conductive feature; and 
 depositing a conductive material in the opening, thereby forming a conductive structure landing on the conductive feature. 
 
     
     
       8. The method of  claim 7 , wherein the conductive feature includes a reflective layer coated on a bulk metal, further comprising:
 partially etching the reflective layer to expose the bulk metal such that the conductive structure lands on the bulk metal. 
 
     
     
       9. The method of  claim 7 , further comprising:
 prior to the depositing of the resist layer, partially recessing a portion of the dielectric layer to form a trench above the conductive feature, wherein the resist layer fills the trench. 
 
     
     
       10. The method of  claim 1 , wherein the radiation is one of a deep ultraviolet (DUV) radiation, an extreme ultraviolet (EUV) radiation, and an electron-beam (E-beam) radiation. 
     
     
       11. A method for lithography patterning, comprising:
 forming a first conductive feature in a top portion of a substrate; 
 forming a dielectric layer over the substrate; 
 partially recessing the dielectric layer to form a trench above the first conductive feature; 
 coating a resist layer over the dielectric layer, the resist layer filling the trench; 
 exposing the resist layer in a radiation, wherein an incident exposure dose of the radiation is configured such that a latent patent is formed in the trench; 
 developing the resist layer to form an opening in the resist layer; 
 etching the dielectric layer through the opening in the resist layer, thereby extending a portion of the trench through the dielectric layer; and 
 forming a second conductive feature in the trench and in contact with the first conductive feature. 
 
     
     
       12. The method of  claim 11 , wherein a top portion of the first conductive feature includes a reflective layer. 
     
     
       13. The method of  claim 12 , wherein the reflective layer includes a plurality of alternating first material layers and second material layers. 
     
     
       14. The method of  claim 12 , further comprising:
 partially etching the reflective layer to expose a bottom portion of the first conducive feature. 
 
     
     
       15. The method of  claim 11 , wherein the incident exposure dose of the radiation is configured to be less than an exposure threshold of the resist layer while a sum of the incident exposure dose and a reflected exposure dose from a top surface of the first conductive feature is larger than the exposure threshold of the resist layer. 
     
     
       16. The method of  claim 11 , wherein the radiation is a blanket radiation without using a mask. 
     
     
       17. The method of  claim 11 , wherein the radiation is an extreme ultraviolet (EUV) radiation. 
     
     
       18. A semiconductor structure, comprising:
 a substrate; 
 a first conductive feature embedded in a top portion of the substrate, the first conductive feature having a first edge and a second edge opposing the first edge; 
 a dielectric layer over the substrate; and 
 a second conductive feature surrounded by the dielectric layer and in contact with the first conductive feature, the second conductive feature having a first sidewall and a second sidewall opposing the first sidewall, wherein the second sidewall is proximal to the second edge of the first conductive feature and distal to the first edge of the first conductive feature, wherein the first sidewall has a straight profile and is directly above the first conductive feature and horizontally offset from the first edge of the first conductive feature, and wherein the second sidewall has a step profile and a top portion of the step profile is horizontally offset from the second edge of the first conductive feature. 
 
     
     
       19. The semiconductor structure of  claim 18 , wherein the first conductive feature includes a reflective layer, and wherein a bottom portion of the first sidewall is covered by the reflective layer. 
     
     
       20. The semiconductor structure of  claim 18 , wherein a bottom portion of the step profile substantially aligns with the second edge of the first conductive feature.