Memory array with asymmetric bit-line architecture

Abstract

The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.

What is claimed is: 
     
       1. A method of forming an integrated circuit, comprising:
 forming a bit-line structure over a substrate, wherein the bit-line structure comprises a first bit-line layer; 
 forming a patterned mandrel over the bit-line structure; 
 forming one or more spacers along opposing sides of the patterned mandrel; 
 removing the patterned mandrel after forming the one or more spacers; 
 patterning the bit-line structure according to the one or more spacers after removing the patterned mandrel to define a plurality of bit-line stacks, wherein the plurality of bit-line stacks comprise a first bit-line stack, a second bit-line stack, and a third bit-line stack, the first bit-line stack is a closest bit-line stack to a first side of the second bit-line stack and the third bit-line stack is a closest bit-line stack to a second side of the second bit-line stack; 
 forming a data storage structure over the plurality of bit-line stacks; 
 forming a selector over the data storage structure; 
 forming a word-line over the selector, wherein the word-line extends over the plurality of bit-line stacks; and 
 wherein the second bit-line stack is separated from the first bit-line stack by a first distance and is separated from the third bit-line stack by a second distance that is larger than the first distance. 
 
     
     
       2. The method of  claim 1 , wherein the bit-line structure further comprises:
 a dielectric material disposed over an upper surface of the first bit-line layer; and 
 a second bit-line layer disposed over an upper surface of the dielectric material. 
 
     
     
       3. The method of  claim 1 , wherein the plurality of bit-line stacks respectively comprise a first bit-line vertically separated from a second bit-line by a dielectric material covering a top surface of the first bit-line. 
     
     
       4. A method of forming an integrated circuit, comprising:
 forming a bit-line structure over a substrate, wherein the bit-line structure comprises a plurality of bit-line layers separated by a dielectric; 
 patterning the bit-line structure to form a plurality of bit-line stacks laterally separated from one another, wherein the plurality of bit-line stacks comprise a first bit-line stack, a second bit-line stack, and a third bit-line stack, the first bit-line stack and the third bit-line stack being closest neighboring bit-line stacks to opposing sides of the second bit-line stack; 
 forming a data storage structure along opposing sides of the plurality of bit-line stacks, the data storage structure continuously extending from directly over the first bit-line stack to directly over the second bit-line stack; 
 forming a selector on opposing sides of the data storage structure; 
 forming a word-line over the selector, wherein the word-line is laterally separated from the data storage structure by the selector; and 
 wherein the first bit-line stack is laterally separated from the second bit-line stack by a first distance that is smaller than a second distance between the second bit-line stack and the third bit-line stack. 
 
     
     
       5. The method of  claim 4 , further comprising:
 forming the data storage structure to continuously extend from along the opposing sides of the plurality of bit-line stacks to directly over the plurality of bit-line stacks. 
 
     
     
       6. The method of  claim 4 , wherein the selector both laterally and vertically separates the word-line from the data storage structure. 
     
     
       7. The method of  claim 4 , wherein the selector continuously extends from directly over the first bit-line stack to directly over the second bit-line stack. 
     
     
       8. The method of  claim 4 , wherein the selector comprises an ovonic threshold switch, a binary material, a ternary material, a quaternary material, or a voltage conductive bridge. 
     
     
       9. The method of  claim 4 , further comprising:
 forming a second word-line over the selector, the word-line being separated from the second word-line along a first direction; and 
 wherein the plurality of bit-line stacks are separated along a second direction that is perpendicular to the first direction, the plurality of bit-line stacks continuously extending in the first direction from directly below the word-line to directly below the second word-line. 
 
     
     
       10. A method of forming an integrated circuit, comprising:
 forming a bit-line structure over a substrate, wherein the bit-line structure comprises a plurality of bit-line layers separated by a dielectric; 
 patterning the bit-line structure to form a first bit-line stack, a second bit-line stack, and a third bit-line stack; 
 forming a data storage structure along sidewalls of the first bit-line stack, the second bit-line stack, and the third bit-line stack; 
 forming a selector on sidewalls of the data storage structure, wherein an upper surface of the selector is completely over tops of the first bit-line stack and the second bit-line stack along an entire distance between the first bit-line stack and the second bit-line stack; and 
 forming a word-line over the selector and directly between the sidewalls of the first bit-line stack and the third bit-line stack, wherein the word-line has a lower surface that continuously extends from directly over the first bit-line stack to directly over the second bit-line stack. 
 
     
     
       11. The method of  claim 10 , wherein the selector comprises one or more interior surfaces that define a void disposed directly between the first bit-line stack and the second bit-line stack. 
     
     
       12. The method of  claim 10 , wherein the data storage structure comprises one or more interior surfaces that define a void disposed directly between the first bit-line stack and the second bit-line stack. 
     
     
       13. The method of  claim 10 , wherein an entirety of the selector that is laterally between the first bit-line stack and the second bit-line stack is completely vertically above the top of the first bit-line stack. 
     
     
       14. The method of  claim 10 , wherein the word-line is not directly and laterally between the first bit-line stack and the second bit-line stack. 
     
     
       15. The method of  claim 10 , wherein the second bit-line stack and the third bit-line stack are asymmetrically spaced apart from the first bit-line stack. 
     
     
       16. The method of  claim 10 , further comprising:
 forming a mandrel over the bit-line structure; 
 forming one or more spacers along opposing sides of the mandrel; 
 removing the mandrel after forming the one or more spacers; and 
 patterning the bit-line structure according to the one or more spacers after removing the mandrel. 
 
     
     
       17. The method of  claim 16 , further comprising:
 forming a masking layer over the bit-line structure prior to forming the mandrel; 
 patterning the masking layer according to the one or more spacers; and 
 forming the data storage structure over the masking layer after patterning the masking layer. 
 
     
     
       18. The method of  claim 10 , wherein the data storage structure is formed to continuously extend from the sidewalls of the first bit-line stack and the second bit-line stack to over the tops of the first bit-line stack and the second bit-line stack. 
     
     
       19. The method of  claim 10 , wherein the data storage structure and the selector continuously extend over the first bit-line stack, the second bit-line stack, and the third bit-line stack after forming the word-line. 
     
     
       20. The method of  claim 10 , wherein the first bit-line stack has a width that is in a range of between approximately 5 nanometers and approximately 25 nanometers.