Post simulation debug and analysis using a system memory model

Abstract

According to an embodiment, a system and method are provided for constructing an accurate view of memory and events on a simulation platform. The system memory view can be used with a debug and analysis tool to provide post-processing debug, including searching forward and backward in capture time of the stored memory view to analyze the events of the simulation. The memory is constructed by capturing and storing each memory execution transaction, bus transaction, and register transaction during simulation. Changes in simulation platform hardware state may also be captured and stored in a hardware state database, including switches between process threads detected during the simulation that may update a simulator register. The captured events provide observability into the OS processes, the hardware, and the embedded software of the simulation platform.

What is claimed is: 
     
       1. A computer-implemented method, the method comprising:
 capturing, during a simulation of a system model and a system memory model, an execution transaction in response to determining that an execution memory-event is one of reading from the system memory model and writing to the system memory model, wherein the captured execution transaction is expressed as an execution trace message; 
 capturing, during the simulation of the system model, a bus transaction in response to determining that a bus memory event is one of reading from a bus and writing to the bus, wherein the captured bus transaction is expressed as a bus trace message; 
 capturing, during the simulation of the system model, a register transaction in response to determining that a register memory event is one of reading from a register model and writing to the register model, wherein the captured register transaction is expressed as a register trace message; 
 capturing, during the simulation of the system model, switches in processes that cause an update to a memory state; 
 storing, during the simulation of the system model, the execution trace message, the bus trace message, and the register trace message in a memory database, wherein the memory database provides a representation of the system memory model during the simulation of the system model; 
 storing, during the simulation of the system model, the switches in processes that cause an update to a memory state in a hardware state database; 
 accessing, after the simulation of the system model, the register trace message and one of the execution trace message and bus trace message in the memory database; 
 accessing, after the simulation of the system model, a memory state in the hardware state database, wherein the memory database and hardware database provide an accessible representation of the system model; and 
 debugging, after the simulation of the system model, the system model based on the accessed memory state, register trace message and one of the accessed bus trace message and the execution trace message. 
 
     
     
       2. The computer-implemented method of  claim 1 , further comprising parsing, during the simulation of the system model, the execution trace message, the bus trace message, and the register trace message. 
     
     
       3. The computer-implemented method of  claim 2 , further comprising:
 determining if a target device for the bus transaction is being tracked in the memory database; and 
 one of:
 storing the bus trace message in response to determining that the target device for the bus transaction is being tracked in the memory database; and 
 ignoring the bus trace message for the target device in response to determining that the target device for the bus transaction is not being tracked in the memory database. 
 
 
     
     
       4. The computer-implemented method of  claim 2 , wherein the parsing comprises identifying the register associated with the register trace message in a memory map and storing the register trace message at an address in the memory database based on the memory map. 
     
     
       5. The computer-implemented method of  claim 1 , wherein at a start of the simulation of the system model values in the memory database are set to zero or undefined. 
     
     
       6. The computer-implemented method of  claim 1 , wherein at a start of the simulation of the system model given values are loaded into the memory database and associated with addresses of the system memory model. 
     
     
       7. The computer-implemented method of  claim 6 , wherein the memory database is not accessible during the simulation of the system model until the simulation is completed corresponding to a complete memory dump. 
     
     
       8. The computer-implemented method of  claim 1 , further comprising querying, after the simulation of the system model, the memory database with an identifier representing one of a hardware model and a software model of the system model. 
     
     
       9. The computer-implemented method of  claim 1 , further comprising querying, after the simulation of the system model, the memory database to identify a time the simulation of the system memory model had a given value to implement a complex breakpoint. 
     
     
       10. The computer-implemented method of  claim 1 , further comprising capturing, during the simulation of the system model, a change in a hardware model and storing, during the simulation of the system model, the captured change in a hardware state database, wherein for each change during the simulation of the system model updating a program counter (PC) register model and storing the update in the hardware state database. 
     
     
       11. The computer-implemented method of  claim 10 , further comprising stepping through, after the simulation of the system model, one of the memory database and the hardware database, in one of forward in capture time or backward in capture time, to display a series of steps corresponding to one of a software source and a hardware model source performed during the simulation of the system model. 
     
     
       12. The computer-implemented method of  claim 10 , further comprising querying, after the simulation of the system model, the hardware state database to find a PC register value corresponding to a specified software line or function which is associated with one of a program, an operating system, a process, and a thread. 
     
     
       13. The method of  claim 10 , further comprising querying, after the simulation of the system model, the hardware state database for a given value to implement a complex breakpoint in a post-process debugger. 
     
     
       14. The computer-implemented method of  claim 1 , wherein the debugging comprises querying the memory database based on input parameters for data at a given instance of time during the simulation of the system model. 
     
     
       15. The computer-implemented method of  claim 14 , wherein the input parameters comprise: a memory address for corresponding data in the system memory model, a length of the corresponding data, and a time value corresponding to the given instance of time. 
     
     
       16. The computer-implemented method of  claim 14 , further comprising, providing, after the simulation of the system model, on a display the queried data at the given instance of time during the simulation of the system model. 
     
     
       17. The computer-implemented method of  claim 1 , further comprising:
 detecting, during the simulation of the system model, a change in a state of a hardware model, the change in the state corresponding to a switch from a given process to another process by a function of the hardware model, wherein the switch causes an update to a program counter (PC) register model; 
 capturing, during the simulation of the system model, the update to the PC register model; and 
 storing, during the simulation of the system model, the captured update in a hardware state database, wherein the captured update characterize an executing flow of a software or an application program at an instruction level. 
 
     
     
       18. The computer-implemented method of  claim 17 , further comprising searching, after the simulation of the system model, variables stored in the memory database and the hardware state database to identify a breakpoint condition. 
     
     
       19. The computer-implemented method of  claim 1 , further comprising:
 capturing, during the simulation of the system model, state changes of processor register models; and 
 storing, during the simulation of the system model, the captured state changes in a hardware state database. 
 
     
     
       20. The computer-implemented method of  claim 19 , further comprising:
 searching, after the simulation of the system model, the hardware state database to locate a given program counter value associated with a given point in time during the simulation of the system model; 
 retrieving, after the simulation of the system model, values from the memory database associated with the given point in time during the simulation of the system model; 
 retrieving, after the simulation of the system model, values from the hardware state database associated with the given point in time during the simulation of the system model; and 
 generating, after the simulation of the system model, an operating system (OS) process table based on the retrieved values from the memory database and the retrieved values from the hardware database. 
 
     
     
       21. A system comprising:
 a memory to store data comprising machine readable instructions and a system model and a system memory model; 
 a processor configured to access the memory and execute the machine readable instructions to:
 capture, during a simulation of the system model, an execution transaction in response to determining that an execution memory event is one of reading from the system memory model or writing to the system memory model, wherein the captured execution transaction is expressed as an execution trace message; 
 capture, during the simulation of the system model, a bus transaction in response to determining that a bus memory event is one of reading from a bus and writing to the bus, wherein the captured bus transaction is expressed as a bus trace message; 
 capture, during the simulation of the system model, a register transaction in response to determining that a register memory event is one of reading from a register model and writing to the register model, wherein the captured register transaction is expressed as a register trace message; 
 capture, during the simulation of the system model, switches in processes that cause an update to a memory state; 
 track, during the simulation of the system model, in a the memory database, a target device associated with the bus transaction; 
 selectively store, during the simulation of the system model, the bus trace message in the memory database based on whether the target device is being tracked in the memory database 
 store, during the simulation of the system model, the execution trace message, and the register trace message in the memory database, wherein the memory database provides a representation of the system memory model during the simulation of the system model; 
 store, during the simulation of the system model, the switches in processes that cause an update to a memory state in a hardware state database; 
 access, after the simulation of the system model, in the memory database, the register trace message and one of the execution trace message and bus trace message during a debugging operation; 
 access, after the simulation of the system model, in the hardware state database, a memory state, wherein the memory database and hardware database provide an accessible representation of the system model 
 debugging, after the simulation of the system model, the system model based on the accessed memory state, the register trace message, and one of the accessed bus trace message and the execution trace message. 
 
 
     
     
       22. The system of  claim 21 , wherein the machine-readable instructions further configure, during the simulation of the system model, the processor to parse the execution trace message, the bus trace message, and the register trace message. 
     
     
       23. The system of  claim 22 , wherein the machine-readable instructions further configure, during the simulation of the system model, the processor to:
 determine if the target device for the bus transaction is being tracked in the memory database, and one of:
 store the bus trace message in response to determining that the target device for the bus transaction is being tracked in the memory database; and 
 ignore the bus trace message for the target device in response to determining that the target device for the bus transaction is not being tracked in the memory database. 
 
 
     
     
       24. The system of  claim 22 , wherein the machine-readable instructions further configure, during the simulation of the system model, the processor to determine the register associated with the register trace message in a memory map and store the register trace message at an address in the memory database based on the memory map. 
     
     
       25. The system of  claim 21 , wherein the debugger is further configured to query, after the simulation of the system model, the memory database with an identifier representing one of a hardware component and a software component of the system model. 
     
     
       26. The system of  claim 21 , wherein the debugger is further configured to query, after the simulation of the system model, the memory database to identify a time the simulation of the system model had a given value to implement a complex breakpoint. 
     
     
       27. The system of  claim 21 , wherein the memory further comprises a hardware state database to store a change in a hardware model during the simulation of the system model, wherein the machine-readable instructions further configure, during the simulation of the system model, the processor to update a program counter (PC) register model for each change during the simulation of the system model and store the update in the hardware state database. 
     
     
       28. The system of  claim 27 , wherein the debugger is further configured to query, after the simulation of the system model, the hardware state database for a given value to implement a complex breakpoint. 
     
     
       29. The system of  claim 28 , wherein the debugger is further configured to step through, after the simulation of the system model, one of the memory database and the hardware state database, in one of forward in capture time and backward in capture time, to display a series of steps corresponding to one of a software source and a hardware model source performed during the simulation of the system model.