Preventing gate-to-contact bridging by reducing contact dimensions in FinFET SRAM

Abstract

A static random access memory (SRAM) cell includes a first gate and a second gate each extending in a first direction. A first gap separates the first gate from the second gate in the first direction. The SRAM cell includes a Vcc contact extending in the first direction. A second gap separates the Vcc contact and the first gate in a second direction perpendicular to the first direction. No segment of the Vcc contact overlaps with the first gap in the first direction. The SRAM cell includes a Vss contact extending in the first direction. A third gap separates the Vss contact from the first gate in the second direction. A segment of the Vss contact is disposed to the first gap. The Vss contact is smaller than the Vcc contact in the second direction.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 an elongated gate structure extending in a first direction, wherein the elongated gate structure has a first end portion, a second end portion, and a third portion disposed between the first end portion and the second end portion; 
 a first conductive contact extending in the first direction, the first conductive contact being disposed adjacent to the third portion of the elongated gate structure, wherein the first conductive contact has a first dimension measured in the first direction and a second dimension measured in a second direction perpendicular to the first direction; 
 a second conductive contact extending in the first direction, the second conductive contact being disposed adjacent to the first end portion of the elongated gate structure, wherein the second conductive contact has an inwardly tapered top view profile, wherein the second conductive contact has a third dimension measured in the first direction and a fourth dimension measured in the second direction, wherein the first dimension is less than the third dimension, and wherein the second dimension is greater than the fourth dimension; and 
 a plurality of fin structures that includes a first fin structure and a second fin structure, wherein the first fin structure intersects with the elongated gate structure and with the first conductive contact in a top view, wherein the second fin structure intersects with the elongated gate structure and with the second conductive contact in a top view, wherein the first fin structure and the second fin structure each extend in the second direction, and wherein the first fin structure is separated from the second fin structure in the first direction; 
 wherein the first conductive contact is a Vcc contact of a Static Random Access Memory (SRAM) cell that includes a pull-up (PU) transistor, a pull-down (PD) transistor, and a pass-gate (PG) transistor, wherein the second conductive contact is a Vss contact of the SRAM cell, wherein the second conductive contact overlaps with a greater number of the fin structures than the first conductive contact, and wherein the elongated gate structure is a gate of: the PU transistor, the PD transistor, or the PG transistor. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein a non-end portion of the second conductive contact is disposed adjacent to the first end portion of the elongated gate structure. 
     
     
       3. The semiconductor device of  claim 1 , further comprising: a third conductive contact extending in the first direction, the third conductive contact being disposed adjacent to the second end portion of the elongated gate structure, wherein the third conductive contact has a fifth dimension measured in the first direction and a sixth dimension measured in the second direction, wherein the first dimension is less than the fifth dimension, and wherein the second dimension is greater than the sixth dimension. 
     
     
       4. The semiconductor device of  claim 3 , wherein the fourth dimension is less than the sixth dimension. 
     
     
       5. The semiconductor device of  claim 3 , wherein:
 the first conductive contact includes the Vcc contact of the SRAM cell; 
 the second conductive contact includes the Vss contact of the SRAM cell; 
 the third conductive contact includes a node contact of the SRAM cell; 
 the node contact is located on a first side of the elongated gate structure; and 
 the Vcc contact and the Vss contact are located on a second side of the elongated gate structure opposite the first side. 
 
     
     
       6. The semiconductor device of  claim 5 , wherein the elongated gate structure is a first elongated gate structure, and wherein the semiconductor device further comprises:
 a second elongated gate structure extending in the first direction, wherein the second elongated gate structure is separated from the first elongated gate structure by a gap; and 
 a bit-line (BL) contact of the SRAM cell disposed adjacent to the second elongated gate structure but not to the first elongated gate structure; 
 wherein: 
 the BL contact has a seventh dimension measured in the first direction and an eighth dimension measured in the second direction; 
 the seventh dimension is less than the third dimension and the fifth dimension; and 
 the eighth dimension is greater than the fourth dimension and the sixth dimension. 
 
     
     
       7. The semiconductor device of  claim 1 , wherein the second dimension is greater than the fourth dimension by at least about 0.5 nanometers. 
     
     
       8. The semiconductor device of  claim 1 , wherein the elongated gate structure has a first boundary and a second boundary that each extend in the first direction in the top view, and both the first fin structure and the second fin structure extend beyond the first boundary and the second boundary of the elongated gate structure in the top view. 
     
     
       9. The semiconductor device of  claim 1 , wherein:
 the second conductive contact has a first end portion, a second end portion, and a middle portion disposed between the first end portion and the second end portion; and 
 the middle portion is inwardly tapered with respect to the first end portion and the second end portion. 
 
     
     
       10. A semiconductor device, comprising:
 an elongated gate structure extending in a first direction, wherein the elongated gate structure has a first end portion, a second end portion, and a third portion disposed between the first end portion and the second end portion; 
 a first conductive contact extending in the first direction, the first conductive contact being disposed adjacent to the third portion of the elongated gate structure, wherein the first conductive contact has a first dimension measured in the first direction and a second dimension measured in a second direction perpendicular to the first direction; 
 a second conductive contact extending in the first direction, the second conductive contact being disposed adjacent to the first end portion of the elongated gate structure, wherein the second conductive contact has an inwardly tapered top view profile, wherein the second conductive contact has a third dimension measured in the first direction and a fourth dimension measured in the second direction, wherein the first dimension is less than the third dimension, and wherein the second dimension is greater than the fourth dimension; and 
 a plurality of fin structures that includes a first fin structure and a second fin structure, wherein the first fin structure intersects with the elongated gate structure and with the first conductive contact in a top view, wherein the second fin structure intersects with the elongated gate structure and with the second conductive contact in a top view, wherein the first fin structure and the second fin structure each extend in the second direction, and wherein the first fin structure is separated from the second fin structure in the first direction; 
 wherein: 
 the first conductive contact is a Vcc contact of a Static Random Access Memory (SRAM) cell that includes a pull-up (PU) transistor, a pull-down (PD) transistor, and a pass-gate (PG) transistor; 
 the second conductive contact is a Vss contact of the SRAM cell; 
 the second conductive contact overlaps with a greater number of the fin structures than the first conductive contact; 
 the elongated gate structure is a gate of: the PU transistor, the PD transistor, or the PG transistor; 
 a portion of the second conductive contact is disposed adjacent to the first end portion of the elongated gate structure; and 
 the elongated gate structure has a first boundary and a second boundary that each extend in the first direction in the top view, and both the first fin structure and the second fin structure extend beyond the first boundary and the second boundary of the elongated gate structure in the top view. 
 
     
     
       11. The semiconductor device of  claim 10 , further comprising: a third conductive contact extending in the first direction, the third conductive contact being disposed adjacent to the second end portion of the elongated gate structure, wherein the third conductive contact has a fifth dimension measured in the first direction and a sixth dimension measured in the second direction, wherein the first dimension is less than the fifth dimension, and wherein the second dimension is greater than the sixth dimension. 
     
     
       12. The semiconductor device of  claim 11 , wherein the fourth dimension is less than the sixth dimension. 
     
     
       13. The semiconductor device of  claim 11 , wherein:
 the first conductive contact includes the Vcc contact of the SRAM cell; 
 the second conductive contact includes the Vss contact of the SRAM cell; 
 the third conductive contact includes a node contact of the SRAM cell; 
 the node contact is located on a first side of the elongated gate structure; and 
 the Vcc contact and the Vss contact are located on a second side of the elongated gate structure opposite the first side. 
 
     
     
       14. The semiconductor device of  claim 13 , wherein the elongated gate structure is a first elongated gate structure, and wherein the semiconductor device further comprises:
 a second elongated gate structure extending in the first direction, wherein the second elongated gate structure is separated from the first elongated gate structure by a gap; and 
 a bit-line (BL) contact of the SRAM cell disposed adjacent to the second elongated gate structure but not to the first elongated gate structure; 
 wherein: 
 the BL contact has a seventh dimension measured in the first direction and an eighth dimension measured in the second direction; 
 the seventh dimension is less than the third dimension and the fifth dimension; and 
 the eighth dimension is greater than the fourth dimension and the sixth dimension. 
 
     
     
       15. The semiconductor device of  claim 10 , wherein the second dimension is greater than the fourth dimension by at least about 0.5 nanometers. 
     
     
       16. The semiconductor device of  claim 10 , wherein:
 the second conductive contact has a first end portion, a second end portion, and a middle portion disposed between the first end portion and the second end portion; and 
 the middle portion is inwardly tapered with respect to the first end portion and the second end portion. 
 
     
     
       17. A semiconductor device, comprising:
 an elongated gate structure extending in a first direction, wherein the elongated gate structure has a first end portion, a second end portion, and a third portion disposed between the first end portion and the second end portion; 
 a first conductive contact extending in the first direction, the first conductive contact being disposed adjacent to the third portion of the elongated gate structure, wherein the first conductive contact has a first dimension measured in the first direction and a second dimension measured in a second direction perpendicular to the first direction; 
 a second conductive contact extending in the first direction, the second conductive contact being disposed adjacent to the first end portion of the elongated gate structure, wherein the second conductive contact has an inwardly tapered top view profile, wherein the second conductive contact has a third dimension measured in the first direction and a fourth dimension measured in the second direction, wherein the first dimension is less than the third dimension, and wherein the second dimension is greater than the fourth dimension; 
 a third conductive contact extending in the first direction, the third conductive contact being disposed adjacent to the second end portion of the elongated gate structure, wherein the third conductive contact has a fifth dimension measured in the first direction and a sixth dimension measured in the second direction, wherein the first dimension is less than the fifth dimension, wherein the second dimension is greater than the sixth dimension, and wherein the fourth dimension is less than the sixth dimension; and 
 a plurality of fin structures that includes a first fin structure and a second fin structure, wherein the first fin structure intersects with the elongated gate structure and with the first conductive contact in a top view, wherein the second fin structure intersects with the elongated gate structure and with the second conductive contact in a top view, wherein the first fin structure and the second fin structure each extend in the second direction, and wherein the first fin structure is separated from the second fin structure in the first direction; 
 wherein the first conductive contact is a Vcc contact of a Static Random Access Memory (SRAM) cell that includes a pull-up (PU) transistor, a pull-down (PD) transistor, and a pass-gate (PG) transistor, wherein the second conductive contact is a Vss contact of the SRAM cell, wherein the second conductive contact overlaps with a greater number of the fin structures than the first conductive contact, and wherein the elongated gate structure is a gate of: the PU transistor, the PD transistor, or the PG transistor. 
 
     
     
       18. The semiconductor device of  claim 17 , wherein:
 the first conductive contact includes the Vcc contact of the SRAM cell; 
 the second conductive contact includes the Vss contact of the SRAM cell; 
 the third conductive contact includes a node contact of the SRAM cell; 
 the node contact is located on a first side of the elongated gate structure; and 
 the Vcc contact and the Vss contact are located on a second side of the elongated gate structure opposite the first side. 
 
     
     
       19. The semiconductor device of  claim 18 , wherein the elongated gate structure is a first elongated gate structure, and wherein the semiconductor device further comprises:
 a second elongated gate structure extending in the first direction, wherein the second elongated gate structure is separated from the first elongated gate structure by a gap; and 
 a bit-line (BL) contact of the SRAM cell disposed adjacent to the second elongated gate structure but not to the first elongated gate structure; 
 wherein: 
 the BL contact has a seventh dimension measured in the first direction and an eighth dimension measured in the second direction; 
 the seventh dimension is less than the third dimension and the fifth dimension; and 
 the eighth dimension is greater than the fourth dimension and the sixth dimension. 
 
     
     
       20. The semiconductor device of  claim 17 , wherein:
 the elongated gate structure has a first boundary and a second boundary that each extend in the first direction in the top view; 
 both the first fin structure and the second fin structure extend beyond the first boundary and the second boundary of the elongated gate structure in the top view; 
 the second conductive contact has a first end portion, a second end portion, and a middle portion disposed between the first end portion and the second end portion; and 
 the middle portion is inwardly tapered with respect to the first end portion and the second end portion.