Semiconductor package

Abstract

A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

What is claimed is: 
     
       1. A semiconductor package, comprising:
 a package substrate; 
 a connection substrate on the package substrate, the connection substrate including a top surface, a bottom surface and a pair of side walls extending between the top surface and the bottom surface, the connection substrate having a recession on a lower corner of at least one of the pair of side walls, the recession facing a top surface of the package substrate; 
 a semiconductor chip on the connection substrate; and 
 a plurality of connection terminals connecting the package substrate to the connection substrate such that the recession is laterally spaced apart from the plurality of connection terminals and relatively closer than the plurality of connection terminals to the at least one of the pair of side walls. 
 
     
     
       2. The semiconductor package of  claim 1 , wherein
 the connection substrate includes a plurality of upper pads on a top surface of the connection substrate and a plurality of lower pads on a bottom surface of the connection substrate, the upper pads connected to the semiconductor chip, and the lower pads connected to the package substrate, and 
 a width of the recession is greater than a distance between a sidewall of the connection substrate and an outermost one of the upper pads. 
 
     
     
       3. The semiconductor package of  claim 2 , wherein the recession vertically overlaps at least one of the upper pads. 
     
     
       4. The semiconductor package of  claim 1 , wherein a width of the recession is in a range of about 100 μm to about 120 μm. 
     
     
       5. The semiconductor package of  claim 1 , wherein the connection substrate includes a chip region and an edge region around the chip region, a sidewall of the connection substrate having a first thickness, and the chip region of the connection substrate having a second thickness, the second thickness being greater than the first thickness. 
     
     
       6. The semiconductor package of  claim 1 , wherein a depth of the recession from a bottom surface of the connection substrate gradually decreases towards the semiconductor chip from a sidewall of the connection substrate. 
     
     
       7. The semiconductor package of  claim 1 , wherein a maximum depth of the recession is in a range of about 70 μm to about 90 μm from a bottom surface of the connection substrate. 
     
     
       8. The semiconductor package of  claim 1 , wherein the recession has a rounded surface. 
     
     
       9. The semiconductor package of  claim 1 , wherein the recession has a stepwise surface. 
     
     
       10. The semiconductor package of  claim 1 , further comprising:
 a plurality of first connection terminals connecting the connection substrate to the semiconductor chip; 
 a first under-fill layer filling a gap between the first connection terminals between the semiconductor chip and the connection substrate; and 
 a second under-fill layer filling a gap between the connection substrate and the package substrate, the recession being in contact with the second under-fill layer. 
 
     
     
       11. The semiconductor package of  claim 1 , further comprising:
 a molding layer on the connection substrate and covering the semiconductor chip, the molding layer having a sidewall aligned with a sidewall of the connection substrate. 
 
     
     
       12. A semiconductor package, comprising:
 a package substrate; 
 a connection substrate on the package substrate, the connection substrate having a recession on a lower corner of the connection substrate, the recession facing a top surface of the package substrate; 
 a semiconductor chip on the connection substrate; and 
 a plurality of connection terminals connecting the package substrate to the connection substrate such that the recession is laterally spaced apart from the plurality of connection terminals, wherein
 the connection substrate includes a chip region and an edge region that surrounds the chip region, the semiconductor chip being on the chip region with the recession defined along the edge region. 
 
 
     
     
       13. The semiconductor package of  claim 1 , wherein
 the connection substrate has a first sidewall and a second sidewall that face each other, 
 the recession includes a first recession adjacent to the first sidewall and a second recession adjacent to the second sidewall, the second recession being mirror-symmetrical with the first recession. 
 
     
     
       14. A semiconductor package, comprising:
 a package substrate; 
 a connection substrate on the package substrate, the connection substrate including a base substrate, a plurality of upper pads on a top surface of the base substrate, a plurality of lower pads on a bottom surface of the base substrate, and a plurality of through vias penetrating the base substrate and connecting the upper pads to the lower pads, the connection substrate including a recession on a lower corner thereof such that a width of the recession is greater than a distance between a sidewall of the connection substrate and an outermost one of the upper pads; 
 a chip stack on the connection substrate, the chip stack including a plurality of first semiconductor chips that are vertically stacked; 
 a second semiconductor chip spaced apart from the chip stack on the connection substrate; 
 a plurality of first connection terminals connecting the connection substrate to the chip stack and connecting the connection substrate to the second semiconductor chip; 
 a first under-fill layer filling a gap between the chip stack and the connection substrate and a gap between the second semiconductor chip and the connection substrate; 
 a molding layer on the connection substrate, the molding layer covering the chip stack and the second semiconductor chip; 
 a plurality of second connection terminals connecting the package substrate to the connection substrate; 
 a second under-fill layer filling a gap between the package substrate and the connection substrate; and 
 a heat radiation structure on the package substrate, the heat radiation structure covering the connection substrate, the chip stack, and the second semiconductor chip. 
 
     
     
       15. The semiconductor package of  claim 14 , wherein the recession vertically overlaps at least one of the upper pads. 
     
     
       16. The semiconductor package of  claim 14 , wherein a depth of the recession from a bottom surface of the connection substrate decreases from the sidewall of the connection substrate. 
     
     
       17. The semiconductor package of  claim 14 , wherein the recession has a rounded surface in contact with the second under-fill layer. 
     
     
       18. The semiconductor package of  claim 14 , wherein a sidewall of the molding layer is aligned with the sidewall of the connection substrate. 
     
     
       19. The semiconductor package of  claim 14 , wherein a top surface of the molding layer, a top surface of the chip stack, and a top surface of the second semiconductor chip are at substantially a same level. 
     
     
       20. The semiconductor package of  claim 14 , wherein
 the width of the recession is between 100 μm to 120 μm, and 
 a maximum depth of the recession from a bottom surface of the connection substrate is between 70 μm to 90 μm.