Semiconductor package

Abstract

A semiconductor package includes a package substrate including a first substrate channel pad and a second substrate channel pad, a chip stack including a plurality of semiconductor chips stacked on the package substrate to be offset in a first direction, wherein first semiconductor chips located on odd layers from among the plurality of semiconductor chips and second semiconductor chips located on even layers from among the plurality of semiconductor chips are offset in a second direction perpendicular to the first direction, each of the first semiconductor chips includes a first chip channel pad, and each of the second semiconductor chips includes a second chip channel pad, first inter-chip connection wires configured to electrically connect the first chip channel pads of the first semiconductor chips to one another, second inter-chip connection wires configured to electrically connect the second chip channel pads of the second semiconductor chips to one another.

What is claimed is: 
     
       1. A semiconductor package comprising:
 a package substrate comprising a first substrate channel pad and a second substrate channel pad; 
 a chip stack comprising a plurality of semiconductor chips stacked on the package substrate to be offset in a first direction, wherein first semiconductor chips located on odd layers from among the plurality of semiconductor chips and second semiconductor chips located on even layers from among the plurality of semiconductor chips are offset in a second direction perpendicular to the first direction, each of the first semiconductor chips comprising a first chip channel pad, and each of the second semiconductor chips comprising a second chip channel pad; 
 first inter-chip connection wires configured to electrically connect the first chip channel pads of the first semiconductor chips to one another; 
 second inter-chip connection wires configured to electrically connect the second chip channel pads of the second semiconductor chips to one another; 
 a first substrate-chip connection wire configured to connect the first chip channel pad of a first semiconductor chip located on a lowest layer from among the first semiconductor chips to the first substrate channel pad; and 
 a second substrate-chip connection wire configured to connect the second chip channel pad of a second semiconductor chip located on a lowest layer from among the second semiconductor chips to the second substrate channel pad. 
 
     
     
       2. The semiconductor package of  claim 1 , wherein, from a planar view, the first chip channel pads of the first semiconductor chips are aligned in the first direction, and the second chip channel pads of the second semiconductor chips are aligned in the first direction. 
     
     
       3. The semiconductor package of  claim 2 , wherein, from a planar view, the first chip channel pads of the first semiconductor chips are spaced apart from the second chip channel pads of the second semiconductor chips in the first and second directions. 
     
     
       4. The semiconductor package of  claim 1 , further comprising:
 a controller comprising a first channel and a second channel separated from each other,
 wherein the first channel of the controller is electrically connected to the first chip channel pads of the first semiconductor chips through the first substrate-chip connection wire and the first inter-chip connection wires, and 
 wherein the second channel of the controller is electrically connected to the second chip channel pads of the second semiconductor chips through the second substrate-chip connection wire and the second inter-chip connection wires. 
 
 
     
     
       5. The semiconductor package of  claim 4 ,
 wherein the first chip channel pads of the first semiconductor chips comprise at least one of an input/output (I/O) pad, a data strobe signal (DQS) pad, a chip enable (CE) pad, a read enable (RE) pad, a write enable (WE) pad, a command latch enable (CLE) pad, an address latch enable (ALE) pad, and a ready/busy (RB) pad, and 
 wherein the second chip channel pads of the second semiconductor chips comprise at least one of an I/O pad, a DQS pad, a CE pad, an RE pad, a WE pad, a CLE pad, an ALE pad, and an RB pad. 
 
     
     
       6. The semiconductor package of  claim 1 ,
 wherein the package substrate comprises a common substrate pad, 
 wherein each of the first semiconductor chips comprises a first common pad, 
 wherein each of the second semiconductor chips comprises a second common pad, and 
 wherein the semiconductor package further comprises:
 third inter-chip connection wires configured to electrically connect the first common pads of the first semiconductor chips to the second common pads of the second semiconductor chips; and 
 a third substrate-chip connection wire configured to electrically connect the first common pad of the first semiconductor chip located on the lowest layer from among the first semiconductor chips to the common substrate pad. 
 
 
     
     
       7. The semiconductor package of  claim 6 ,
 wherein the first common pads of the first semiconductor chips comprise at least one of a Vcc pad and a Vss pad, and 
 wherein the second common pads of the second semiconductor chips comprise at least one of a Vcc pad and a Vss pad. 
 
     
     
       8. The semiconductor package of  claim 7 ,
 wherein, from a planar view, the first common pads of the first semiconductor chips are arranged side by side in the first direction, and the second common pads of the second semiconductor chips are arranged side by side in the first direction, and 
 wherein from a planar view, the first common pads of the first semiconductor chips are spaced apart from the second common pads of the second semiconductor chips in the second direction. 
 
     
     
       9. The semiconductor package of  claim 6 ,
 wherein each of the first semiconductor chips has a pad arrangement in which two first chip channel pads are spaced apart from each other with one first common pad between the two first chip channel pads, and 
 wherein each of the second semiconductor chips has a pad arrangement in which two second chip channel pads are spaced apart from each other with one second common pad between the two second chip channel pads. 
 
     
     
       10. The semiconductor package of  claim 1 , wherein a distance by which the plurality of semiconductor chips are offset in the first direction is about 230 μm to about 400 μm. 
     
     
       11. The semiconductor package of  claim 1 ,
 wherein each of the first semiconductor chips comprises a plurality of first chip channel pads arranged along one edge of the first semiconductor chip, wherein each of the second semiconductor chips comprises a plurality of second chip channel pads arranged along one edge of the second semiconductor chip, and 
 wherein an interval between the plurality of first chip channel pads is equal to an interval between the plurality of second chip channel pads. 
 
     
     
       12. The semiconductor package of  claim 11 , wherein the interval between the plurality of first chip channel pads and the interval between the plurality of second chip channel pads are greater than a distance by which the first semiconductor chips and the second semiconductor chips are offset in the second direction. 
     
     
       13. The semiconductor package of  claim 1 , wherein each of the plurality of semiconductor chips includes a NAND flash memory. 
     
     
       14. The semiconductor package of  claim 1 , wherein each of the first inter-chip connection wires is configured to connect two first semiconductor chips spaced apart from each other with one second semiconductor chip between the two first semiconductor chips. 
     
     
       15. A semiconductor package comprising:
 a package substrate comprising a common substrate pad, a first substrate channel pad, and a second substrate channel pad; 
 a plurality of semiconductor chips stacked on the package substrate to be offset in a first direction, each of the plurality of semiconductor chips comprising a common pad and a channel pad; 
 first inter-chip connection wires configured to electrically connect the channel pads of semiconductor chips located on odd layers from among the plurality of semiconductor chips to one another; 
 second inter-chip connection wires configured to electrically connect the channel pads of semiconductor chips located on even layers from among the plurality of semiconductor chips to one another; 
 third inter-chip connection wires configured to electrically connect the common pads of the plurality of semiconductor chips to one another; 
 a first substrate-chip connection wire configured to electrically connect the channel pad of a semiconductor chip located on a lowest layer from among the semiconductor chips located on the odd layers to the first substrate channel pad; 
 a second substrate-chip connection wire configured to electrically connect the channel pad of a semiconductor chip located on a lowest layer from among the semiconductor chips located on the even layers to the second substrate channel pad; 
 a third substrate-chip connection wire configured to electrically connect the common pad of the semiconductor chip located on the lowest layer from among the semiconductor chips located on the odd layers to the common substrate pad; and 
 a controller mounted on the package substrate and comprising a first channel and a second channel separated from each other, 
 wherein the first channel of the controller is electrically connected to the semiconductor chips located on the odd layers through the first substrate-chip connection wire and the first inter-chip connection wires, and 
 wherein the second channel of the controller is electrically connected to the semiconductor chips located on the even layers through the second substrate-chip connection wire and the second inter-chip connection wires. 
 
     
     
       16. The semiconductor package of  claim 15 ,
 wherein a number of first inter-chip connection wires is equal to a number obtained by subtracting 1 from a total number of the semiconductor chips located on the odd layers, 
 wherein a number of second inter-chip connection wires is equal to a number obtained by subtracting 1 from a total number of the semiconductor chips located on the even layers, and 
 wherein a number of third inter-chip connection wires is equal to a number obtained by subtracting 1 from a total number of the plurality of semiconductor chips. 
 
     
     
       17. The semiconductor package of  claim 15 , wherein each of the first inter-chip connection wires extends in the first direction, and each of the second inter-chip connection wires extends in the first direction. 
     
     
       18. The semiconductor package of  claim 15 , wherein the channel pads of the semiconductor chips located on the odd layers are spaced apart from the channel pads of the semiconductor chips located on the even layers in the first direction and the second direction perpendicular to the first direction. 
     
     
       19. The semiconductor package of  claim 15 ,
 wherein the channel pads of the plurality of semiconductor chips correspond to input/output (I/O) pads, data strobe signal (DQS) pads, chip enable (CE) pads, read enable (RE) pads, write enable (WE) pads, command latch enable (CLE) pads, address latch enable (ALE) pads, or ready/busy (RB) pads, and 
 wherein the common pads of the plurality of semiconductor chips correspond to Vcc pads or Vss pads. 
 
     
     
       20. A semiconductor package comprising:
 a package substrate comprising a common substrate pad, a first substrate channel pad, and a second substrate channel pad; 
 a plurality of semiconductor chips stacked on the package substrate in a vertical direction, each of the plurality of semiconductor chips comprising a common pad and a channel pad; 
 first inter-chip connection wires configured to electrically connect the channel pads of semiconductor chips located on odd layers from among the plurality of semiconductor chips to one another; 
 second inter-chip connection wires configured to electrically connect the channel pads of semiconductor chips located on even layers from among the plurality of semiconductor chips to one another; 
 third inter-chip connection wires configured to electrically connect the common pads of the plurality of semiconductor chips to one another; 
 a first substrate-chip connection wire configured to connect the channel pad of a semiconductor chip located on a lowest layer from among the semiconductor chips located on the odd layers to the first substrate channel pad; 
 a second substrate-chip connection wire configured to connect the channel pad of a semiconductor chip located on a lowest layer from among the semiconductor chips located on the even layers to the second substrate channel pad; 
 a third substrate-chip connection wire configured to electrically connect the common pad of the semiconductor chip located on the lowest layer from among the semiconductor chips located on the odd layers to the common substrate pad; and 
 a controller mounted on the package substrate, electrically connected to the semiconductor chips located on the odd layers through the first substrate-chip connection wire and the first inter-chip connection wires, and electrically connected to the semiconductor chips located on the even layers through the second substrate-chip connection wire and the second inter-chip connection wires, 
 wherein a number of first inter-chip connection wires is equal to a number obtained by subtracting 1 from a total number of the semiconductor chips located on the odd layers, 
 wherein a number of second inter-chip connection wires is equal to a number obtained by subtracting 1 from a total number of the semiconductor chips located on the even layers, and 
 wherein a number of third inter-chip connection wires is equal to a number obtained by subtracting 1 from a total number of the plurality of semiconductor chips.