Semiconductor device with through semiconductor via and method for fabricating the same

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, a through semiconductor via, and an insulation layer. The first semiconductor structure includes a first circuit layer and a first main bonding layer in the first circuit layer and substantially coplanar with a front face of the first circuit layer. The second semiconductor structure includes a second circuit layer on the first circuit layer and a second main bonding layer in the second circuit layer, and topologically aligned with and contacted to the first main bonding layer. The through semiconductor via is along the second semiconductor structure and the first and second main bonding layer, and extending to the first circuit layer. The insulation layer is positioned on a sidewall of the through semiconductor via.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a first semiconductor structure comprising a first circuit layer positioned on a first substrate, and a first main bonding layer positioned in the first circuit layer, wherein a top surface of the first main bonding layer is substantially coplanar with a front face of the first circuit layer; 
 a second semiconductor structure comprising a second circuit layer positioned on the first circuit layer, a second substrate positioned on the second circuit layer, and a second main bonding layer positioned in the second circuit layer, and aligned with and contacted to the first main bonding layer; 
 a through semiconductor via positioned in the second semiconductor structure and the first main bonding layer, extending to the first circuit layer, and physically and electrically coupled to a corresponding conductive line in the first circuit layer; and 
 an insulation layer conformally formed on a sidewall of the through semiconductor via, the insulation layer positioned between the second semiconductor structure and the through semiconductor via, between the first main bonding layer and the through semiconductor via, and between the first circuit layer and the through semiconductor via; 
 wherein the insulation layer includes an opening to expose at least partially the corresponding conductive line in the first circuit layer. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein a horizontal cross-sectional area of the through semiconductor via positioned in the second semiconductor structure is greater than a horizontal cross-sectional area of the through semiconductor via positioned in the first main bonding layer. 
     
     
       3. The semiconductor device of  claim 2 , wherein a horizontal cross-sectional area of the through semiconductor via positioned in the second substrate is greater than a horizontal cross-sectional area of the through semiconductor via positioned in the second main bonding layer. 
     
     
       4. The semiconductor device of  claim 2 , further comprising a first sub-bonding layer and a second sub-bonding layer;
 wherein the first sub-bonding layer is positioned in the first circuit layer and a top surface of the first sub-bonding layer is substantially coplanar with the front face of the first circuit layer, and the second sub-bonding layer is positioned in the second circuit layer and a bottom surface of the second sub-bonding layer is substantially coplanar with the front face of the first circuit layer; wherein the first sub-bonding layer and the second sub-bonding layer are aligned and contacted to each other. 
 
     
     
       5. The semiconductor device of  claim 4 , wherein a horizontal cross-sectional area of the first sub-bonding layer is less than a horizontal cross-sectional area of the first main bonding layer and a horizontal cross-sectional area of the second sub-bonding layer is less than a horizontal cross-sectional area of the second main bonding layer. 
     
     
       6. The semiconductor device of  claim 2 , wherein a sidewall of the through semiconductor via positioned in the first main bonding layer is tapered. 
     
     
       7. The semiconductor device of  claim 2 , wherein a ratio between the horizontal cross-sectional area of the through semiconductor via positioned in the second semiconductor structure and a horizontal cross-sectional area of the second substrate is between about 2% and about 10%. 
     
     
       8. The semiconductor device of  claim 2 , wherein a ratio between the horizontal cross-sectional area of the through semiconductor via positioned in the second semiconductor structure and a horizontal cross-sectional area of the second main bonding layer is between about 30% and about 70%. 
     
     
       9. The semiconductor device of  claim 2 , wherein the through semiconductor via is electrically coupled to an external power source. 
     
     
       10. The semiconductor device of  claim 2 , further comprising a connector positioned on the through semiconductor via. 
     
     
       11. The semiconductor device of  claim 8 , wherein a layout of the first circuit layer is different from a layout of the second circuit layer. 
     
     
       12. The semiconductor device of  claim 11 , wherein the layout of the first circuit layer and the layout of the second circuit layer are symmetrical. 
     
     
       13. The semiconductor device of  claim 2 , wherein a thickness of the first substrate is greater than or equal to a thickness of the second substrate. 
     
     
       14. The semiconductor device of  claim 2 , further comprising a thermal dissipation layer positioned below the first substrate, wherein the thermal dissipation layer comprises vertically oriented graphite and carbon nanotubes. 
     
     
       15. The semiconductor device of  claim 14 , further comprising an attachment layer positioned between the thermal dissipation layer and the first substrate, wherein the attachment layer comprises die attach film, silver paste, or the like. 
     
     
       16. A method for fabricating a semiconductor device, comprising:
 providing a first semiconductor structure comprising a first circuit layer on a first substrate, and a first main bonding layer in the first circuit layer; forming a first opening to expose at least partially a corresponding first conductive line in the first circuit layer; 
 providing a second semiconductor structure comprising a second circuit layer on a second substrate, and a second main bonding layer in the second circuit layer; forming a second opening to expose at least partially the second substrate; 
 flipping the second semiconductor structure and bonding the second circuit layer onto the first circuit layer through a hybrid bonding; wherein the first main bonding layer and the second main bonding layer are aligned and contacted to each other; wherein the first opening and the second opening are aligned and connected to each other to form a first space; and 
 forming a third opening positioned in the second substrate and connected to the first space to form a via opening; conformally forming an insulation layer on a sidewall of the via opening; thereby providing a through semiconductor via in the via opening. 
 
     
     
       17. The method for fabricating the semiconductor device of  claim 16 , wherein a horizontal cross-sectional area of the first opening is less than a horizontal cross-sectional area of the second opening. 
     
     
       18. The method for fabricating the semiconductor device of  claim 16 , wherein a horizontal cross-sectional area of the second main bonding layer is less than a horizontal cross-sectional area of the first main bonding layer after the formation of the first opening and the second opening. 
     
     
       19. The method for fabricating the semiconductor device of  claim 16 , wherein the step of forming the insulation layer comprises:
 conformally forming a layer of insulation material on the sidewall and a bottom surface of the via opening; and 
 removing the layer of insulation material on the bottom surface of the via opening to expose at least partially the corresponding first conductive line. 
 
     
     
       20. The method for fabricating the semiconductor device of  claim 16 , further comprising a step of performing a thermal annealing process after the bonding of the second circuit layer onto the first circuit layer, wherein a process temperature of the thermal annealing process is between about 25° C. and about 400° C.