Redistribution layer features

Abstract

Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.

What is claimed is: 
     
       1. A semiconductor structure, comprising:
 a contact feature in a dielectric layer; 
 a passivation structure over the dielectric layer; 
 a conductive feature over the passivation structure; 
 a seed layer disposed between the conductive feature and the passivation structure; 
 a protecting layer disposed along sidewalls of the conductive feature; and 
 a passivation layer extending conformally along a top surface of the conductive feature and sidewalls of the protecting layer. 
 
     
     
       2. The semiconductor structure of  claim 1 , wherein the contact feature and the conductive feature comprise copper (Cu). 
     
     
       3. The semiconductor structure of  claim 1 , wherein the seed layer comprises tantalum nitride (TaN), tantalum (Ta), or copper (Cu). 
     
     
       4. The semiconductor structure of  claim 1 , further comprising a metal-insulator-metal (MIM) capacitor embedded in the passivation structure. 
     
     
       5. The semiconductor structure of  claim 1 , wherein the passivation layer comprises silicon oxide or undoped silica glass (USG). 
     
     
       6. The semiconductor structure of  claim 1 , wherein the protecting layer is a single layer and comprises silicon nitride. 
     
     
       7. The semiconductor structure of  claim 1 ,
 wherein the protecting layer comprises a first layer in contact with the conductive feature and a second layer spaced apart from the conductive feature by the first layer, 
 wherein the first layer comprises silicon nitride, and 
 wherein the second layer comprises silicon oxide. 
 
     
     
       8. The semiconductor structure of  claim 1 ,
 wherein the protecting layer comprises a first layer in contact with the conductive feature, a second layer spaced apart from the conductive feature by the first layer, and a third layer spaced apart from the conductive feature by the first layer and the second layer 
 wherein the first layer comprises silicon nitride, 
 wherein the second layer comprises silicon oxide, 
 wherein the third layer comprises silicon nitride. 
 
     
     
       9. A semiconductor device, comprising:
 a contact feature; 
 a passivation structure over the contact feature; 
 a metal-insulator-metal (MIM) structure embedded in the passivation structure; 
 a conductive feature over the passivation structure and extending through the passivation structure to electrically couple to the contact feature; 
 a seed layer extending along an interface between the conductive feature and the passivation structure; 
 a protecting layer disposed along sidewalls of the conductive feature over the passivation structure; and 
 a passivation layer over the conductive feature and extending along sidewalls of the protecting layer, 
 wherein the passivation layer is in contact with sidewalls of the seed layer and a top surface of the passivation structure. 
 
     
     
       10. The semiconductor device of  claim 9 , wherein a portion of the seed layer is disposed below the protecting layer. 
     
     
       11. The semiconductor device of  claim 9 , wherein the contact feature and the conductive feature comprise copper (Cu). 
     
     
       12. The semiconductor device of  claim 9 , wherein the seed layer comprises tantalum nitride (TaN), tantalum (Ta), or copper (Cu). 
     
     
       13. The semiconductor device of  claim 9 , wherein the protecting layer is a single layer and comprises silicon nitride. 
     
     
       14. The semiconductor device of  claim 9 ,
 wherein the protecting layer comprises a first layer in contact with the conductive feature and a second layer spaced apart from the conductive feature by the first layer, 
 wherein the first layer comprises silicon nitride, and 
 wherein the second layer comprises silicon oxide. 
 
     
     
       15. A semiconductor structure, comprising:
 a metal-insulator-metal (MIM) structure comprising:
 a plurality of conductive plates, and 
 a plurality of insulator layers interleaving the plurality of conductive plates; 
 
 a dielectric layer disposed over the MIM structure; 
 a conductive feature comprising:
 a lower portion extending through the dielectric layer and at least one of the plurality of conductive plates in the MIM structure, and 
 an upper portion disposed over the lower portion and the dielectric layer; 
 
 a seed layer extending along an interface between the upper portion of the conductive feature and the dielectric layer; 
 a protecting layer disposed along sidewalls of the upper portion of the conductive feature; and 
 a passivation layer over and in contact with sidewalls of the protecting layer, sidewalls of the seed layer, and a top surface of the upper portion of the conductive feature. 
 
     
     
       16. The semiconductor structure of  claim 15 , wherein the seed layer continuously extends between the lower portion of the conductive feature and at least one of the plurality of conductive plates. 
     
     
       17. The semiconductor structure of  claim 15 , wherein the conductive feature comprise copper (Cu). 
     
     
       18. The semiconductor structure of  claim 15 , wherein the seed layer comprises tantalum nitride (TaN), tantalum (Ta), or copper (Cu). 
     
     
       19. The semiconductor structure of  claim 15 , wherein the protecting layer is a single layer and comprises silicon nitride. 
     
     
       20. The semiconductor structure of  claim 15 ,
 wherein the protecting layer comprises a first layer in contact with the conductive feature and a second layer spaced apart from the conductive feature by the first layer, 
 wherein the first layer comprises silicon nitride, and 
 wherein the second layer comprises silicon oxide.