Semiconductor-on-insulator (SOI) substrate and method for forming

Abstract

Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.

What is claimed is: 
     
       1. A semiconductor-on-insulator (SOI) substrate comprising:
 a handle substrate; 
 a device layer overlying a central portion of the handle substrate, but not overlying a peripheral region of the handle substrate; and 
 an insulator layer separating the handle substrate from the device layer, the insulator layer meeting the device layer at a first interface and meeting the handle substrate at a second interface, wherein the insulator layer comprises a getter material having a getter concentration profile; 
 wherein the handle substrate contains getter material and has a handle getter concentration profile, the handle getter concentration profile having a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentrations; 
 wherein the insulator layer includes a central insulator region that is directly between the central portion of the handle substrate and the device layer, and includes a peripheral insulator region that is directly over the peripheral region of the handle substrate, wherein the central insulator region has a central region thickness as measured perpendicular from the first interface to the second interface and wherein the peripheral insulator region has a peripheral region thickness as measured perpendicular from an upper surface of the handle substrate to an upper surface of the peripheral insulator region, the central region thickness being greater than the peripheral region thickness. 
 
     
     
       2. The SOI substrate of  claim 1 :
 wherein the device layer is disposed over an upper surface of the handle substrate; and 
 wherein the insulator layer covers the upper surface of the handle substrate to separate the upper surface of the handle substrate from the device layer, covers a lower surface of the handle substrate, and covers sidewalls of the handle substrate. 
 
     
     
       3. The SOI substrate of  claim 2 , wherein the getter concentration profile has a first peak concentration at the first interface, a second peak concentration at the second interface and a trough concentration at a location between the first interface and the second interface, the trough concentration being less than each of the first peak concentration and the second peak concentration. 
     
     
       4. The SOI substrate of  claim 3 , wherein the second interface corresponds to a point where the upper surface of the handle substrate meets the insulator layer, and the first peak concentration is less than the second peak concentration. 
     
     
       5. The SOI substrate of  claim 4 , wherein the getter material is present in the device layer at a first concentration, and is present in the handle substrate at a second concentration, the first concentration being less than the second concentration. 
     
     
       6. The SOI substrate of  claim 3 , wherein the first peak concentration is equal to the second peak concentration. 
     
     
       7. The SOI substrate of  claim 6 , wherein the insulator layer is confined between the device layer and the handle substrate, such that a lowermost surface of the insulator layer corresponds to an uppermost surface of the handle substrate, and an uppermost surface of the insulator layer corresponds to a lowermost surface of the device layer. 
     
     
       8. The SOI substrate of  claim 3 , wherein the first peak concentration and the second peak concentration are each at least 1×10 18  atoms/cm 3  of chlorine or fluorine, and the trough concentration ranges between 1×10 14  atoms/cm 3  and 2×10 17  atoms/cm 3 . 
     
     
       9. The SOI substrate of  claim 1 , wherein the getter material comprises chlorine or fluorine. 
     
     
       10. A method for forming a semiconductor-on-insulator (SOI) substrate, the method comprising:
 receiving a handle substrate; 
 receiving a semiconductor device substrate; 
 wherein an insulating layer is disposed on a face of at least one of the handle substrate and the semiconductor device substrate, the insulating layer including metal contaminants; 
 bonding the handle substrate to the semiconductor device substrate such that the insulating layer separates the handle substrate from the semiconductor device substrate; and 
 wherein before the handle substrate is bonded to the semiconductor device substrate, the insulating layer is subjected to a gettering process in which a gettering material is provided in the insulating layer to getter away the metal contaminants; 
 processing the insulating layer to establish a peripheral region of the insulating layer and a central region of the insulating layer which are over the handle substrate, wherein the peripheral region has a peripheral region thickness as measured perpendicular from a top surface of the peripheral region to an upper surface of the handle substrate and the central region has a central region thickness as measured perpendicular from an interface between the semiconductor device substrate and the insulating layer to the upper surface of the handle substrate, the central region thickness being greater than the peripheral region thickness. 
 
     
     
       11. The method of  claim 10 , wherein the gettering process comprises:
 subjecting the insulating layer to an atmosphere heated to a temperature ranging between 950° C. and 1150° C. for between 0.5 hours and 27 hours, wherein the atmosphere includes trans-1, 2-dichlorethylene, nitrogen, and oxygen. 
 
     
     
       12. The method of  claim 11 , wherein after the gettering process, the insulating layer has a chlorine concentration profile having a first peak chlorine concentration ranging from 5×10 18  atoms/cm 3  to 2×10 21  atoms/cm 3  at an outer surface region of the insulating layer and a minimum chlorine concentration less than the first peak chlorine concentration in an interior region of the insulating layer. 
     
     
       13. The method of  claim 10 , wherein the gettering process comprises:
 subjecting the insulating layer to a first atmosphere that is heated to a first temperature ranging between 700° C. and 950° C. for 5 minutes to 30 minutes, wherein the first atmosphere includes hydrochloric acid; and 
 after the insulating layer is subjected to the first atmosphere, subjecting the insulating layer to a second atmosphere heated to a temperature ranging between 950° C. and 1100° C. for between 0.5 hours and 24 hours, wherein the second atmosphere includes hydrogen, nitrogen, and oxygen. 
 
     
     
       14. The method of  claim 13 , wherein after the gettering process, the insulating layer has a chlorine concentration profile having a first peak chlorine concentration ranging from 5×10 18  atoms/cm 3  to 2×10 21  atoms/cm 3  at an outer surface region of the insulating layer and a minimum chlorine concentration less than the first peak chlorine concentration in an interior region of the insulating layer. 
     
     
       15. The method of  claim 10 , wherein the gettering process comprises:
 subjecting the insulating layer to a first atmosphere that is heated to a first temperature of approximately 400° C. for 5 minutes to 30 minutes, wherein the first atmosphere includes fluorine gas; and 
 after the insulating layer is subjected to the first atmosphere, subjecting the insulating layer to a second atmosphere heated to a temperature ranging between 950° C. and 1100° C. for between 0.5 hours and 24 hours, wherein the second atmosphere includes hydrogen, nitrogen, and oxygen. 
 
     
     
       16. The method of  claim 15 , wherein after the gettering process, the insulating layer has a fluorine concentration profile having a first peak fluorine concentration ranging from 1×10 18  atoms/cm 3  to 1×10 20  atoms/cm 3  at an outer surface region of the insulating layer and a minimum chlorine concentration less than the first peak fluorine concentration in an interior region of the insulating layer. 
     
     
       17. A semiconductor-on-insulator (SOI) wafer comprising:
 a handle substrate including a first circumferential outer edge; 
 a device layer overlying the handle substrate and including a second circumferential outer edge that is concentric with regards to the first circumferential outer edge and bounded by the first circumferential outer edge when viewed from above; and 
 an insulator layer separating the handle substrate from the device layer when viewed in cross-section, wherein the insulator layer comprises a getter material; 
 wherein the insulator layer includes a peripheral region and a central region that are both disposed over the handle substrate, wherein the peripheral region has a peripheral region thickness as measured perpendicular from an upper surface of the peripheral region to an upper surface of the handle substrate and the central region has a central region thickness as measured perpendicular from an interface between the device layer and the insulator layer to the upper surface of the handle substrate, the central region thickness being greater than the peripheral region thickness. 
 
     
     
       18. The SOI wafer of  claim 17 , wherein the second circumferential outer edge of the device layer corresponds to a sidewall step in the insulator layer where the peripheral region meets the central region. 
     
     
       19. The SOI wafer of  claim 17 , further comprising:
 a plurality of semiconductor devices disposed in the device layer; and 
 an interconnect structure comprising vias and metal wires disposed over the device layer, wherein the interconnect structure operably couples two or more of the plurality of semiconductor devices to one another. 
 
     
     
       20. The SOI wafer of  claim 17 , wherein the central region thickness ranges from 0.2 micrometers to 2.5 micrometers, and the peripheral region thickness ranges from 20 angstroms to 6000 angstroms.