Semiconductor package and method of fabricating the same

Abstract

A semiconductor package includes: a lower package: an upper substrate on the lower package: and connection members connecting the lower package to the upper substrate, wherein the lower package includes: a lower substrate; and a lower semiconductor chip, wherein the upper substrate includes: an upper substrate body: upper connection pads combined with the connection members: and auxiliary members extending from the upper substrate body toward the lower substrate, wherein the connection members are arranged in a first horizontal direction to form a first connection member column, wherein the auxiliary members are arranged in the first horizontal direction to form a first auxiliary member column, wherein the first connection member column and the first auxiliary member column are located between a side surface of the lower semiconductor chip and a side surface of the lower substrate, and the first auxiliary member column is spaced apart from the first connection member column.

What is claimed is: 
     
       1. A semiconductor package, comprising:
 a lower package; 
 an upper substrate on the lower package; and 
 a plurality of connection members electrically connecting the lower package to the upper substrate, 
 wherein the lower package comprises:
 a lower substrate; and 
 a lower semiconductor chip on the lower substrate, 
 
 wherein the upper substrate comprises;
 an upper substrate body; 
 upper connection pads provided on the upper substrate body and combined with the plurality of connection members, respectively; and 
 auxiliary members extending from a bottom surface of the upper substrate body toward the lower substrate, wherein the auxiliary members comprise the same insulating material as the upper substrate body, 
 
 wherein the plurality of connection members are arranged in a first horizontal direction to form a first connection member column, 
 wherein the auxiliary members are arranged in the first horizontal direction to form a first auxiliary member column, 
 wherein the first connection member column and the first auxiliary member column are located between a side surface of the lower semiconductor chip and a side surface of the lower substrate, 
 the first auxiliary member column is spaced apart from the first connection member column, in a second horizontal direction crossing the first horizontal direction, 
 wherein, the semiconductor package further comprises a lower mold layer provided on the lower substrate, wherein a side surface of the auxiliary member contacts the lower mold layer. 
 
     
     
       2. The semiconductor package of  claim 1 , wherein each of the auxiliary members is spaced apart from a top surface of the lower substrate. 
     
     
       3. The semiconductor package of  claim 1 , wherein each of the auxiliary members comprises a photo solder resist (PSR). 
     
     
       4. The semiconductor package of  claim 1 , wherein each of the auxiliary members has a circular shape. 
     
     
       5. The semiconductor package of  claim 1 , wherein the lower mold layer at least partially surrounds a side surface of the lower semiconductor chip,
 wherein the lower mold layer overlaps a bottom surface of each of the auxiliary members and at least partially surrounds each of the auxiliary members. 
 
     
     
       6. The semiconductor package of  claim 1 , wherein two adjacent connection members of the plurality of connection members in the first connection member column are spaced apart from each other by a first distance,
 wherein the first connection member column and the first auxiliary member column are spaced apart from each other by a second distance, and 
 the second distance is about 0.5 to about 2 times the first distance. 
 
     
     
       7. The semiconductor package of  claim 1 , wherein the number of the auxiliary members in the first auxiliary member column is equal to the number of the connection members in the first connection member column, and
 each of the auxiliary members in the first auxiliary member column is spaced apart from a corresponding connection member of the plurality of connection members in the first connection member column in the second horizontal direction. 
 
     
     
       8. The semiconductor package of  claim 1 , further comprises a spacer extending from the bottom surface of the upper substrate body toward the lower semiconductor chip. 
     
     
       9. The semiconductor package of  claim 8 , wherein a thickness of each of the auxiliary members is larger than a thickness of the spacer. 
     
     
       10. A semiconductor package, comprising:
 a lower package; 
 an upper package on the lower package; and 
 a plurality of connection members electrically connecting the lower package to the upper package, 
 wherein the lower package comprises:
 a lower substrate; and 
 a lower semiconductor chip on the lower substrate, 
 
 wherein the upper package comprises:
 an upper substrate; and 
 an upper semiconductor chip on the upper substrate, 
 
 wherein the upper substrate comprises:
 an upper substrate body; 
 upper connection pads exposed by a bottom surface of the upper substrate body and are respectively combined with the plurality of connection members; and 
 auxiliary members extending from the bottom surface of the upper substrate body in a first direction, 
 
 wherein the lower substrate comprises:
 a lower substrate body; and 
 lower connection pads exposed by a top surface of the lower substrate body and are respectively combined with the plurality of connection members, 
 
 wherein the plurality of connection members are arranged to form:
 a first connection member column parallel to a second direction crossing the first direction; 
 a first connection member row parallel to a third direction crossing the first direction and the second direction; and 
 a second connection member row parallel to the third direction, 
 
 wherein the first connection member row and the second connection member row are spaced apart from each other in the second direction, 
 wherein the auxiliary members are arranged in the second direction to form a first auxiliary member column spaced apart from the lower semiconductor chip in the third direction, and 
 wherein the first auxiliary member column is spaced apart from the first connection member column in the third direction. 
 
     
     
       11. The semiconductor package of  claim 10 , wherein the first connection member row and the second connection member row are spaced apart from each other by a first distance in the second direction,
 the first connection member column and the first auxiliary member column are spaced apart from each other by a second distance in the third direction, and 
 the second distance is about 0.5 to about 2 times the first distance. 
 
     
     
       12. The semiconductor package of  claim 10 , further comprising a lower mold layer provided on the lower substrate and at least partially surrounding a side surface of the lower semiconductor chip, and
 wherein the lower mold layer is in contact with a bottom surface of each of the auxiliary members and a side surface of each of the auxiliary members and at least partially surrounds each of the auxiliary members. 
 
     
     
       13. The semiconductor package of  claim 10 , wherein each of the auxiliary members has a cylindrical shape or a cuboid shape. 
     
     
       14. The semiconductor package of  claim 10 , wherein each of the auxiliary members comprises a photo solder resist (PSR) or a metal. 
     
     
       15. A method of fabricating a semiconductor package, comprising:
 preparing a lower structure; 
 preparing an upper structure; and 
 combining the upper structure to the lower structure, 
 wherein the upper structure comprises a substrate, 
 wherein the substrate comprises:
 a substrate body; 
 a connection pad on a bottom surface of the substrate body; and 
 an auxiliary member extending from the bottom surface of the substrate body, 
 
 wherein the combining of the upper structure to the lower structure comprises:
 combining an upper solder ball to the connection pad on the bottom surface of the substrate body; 
 coating the upper solder ball with a flux; and 
 combining the upper structure, on which the upper solder ball coated with the flux is provided, with the lower structure, after coating the upper solder ball with the flux, 
 
 wherein the upper solder ball and the auxiliary member are spaced apart from each other, and 
 wherein the coating of the upper solder ball with the flux comprises forming the flux in a region between the upper solder ball and the auxiliary member. 
 
     
     
       16. The method of  claim 15 , wherein the coating of the upper solder ball with the flux comprises forming the flux to cover a bottom surface of the auxiliary member and a side surface of the auxiliary member. 
     
     
       17. The method of  claim 15 , wherein the coating of the upper solder ball with the flux is performed in a dipping manner. 
     
     
       18. The method of  claim 17 , wherein the coating of the upper solder ball with the flux comprises moving the upper structure toward a flux container containing the flux such that a bottom surface of the auxiliary member is immersed into the flux in the flux container. 
     
     
       19. The method of  claim 15 , wherein a thickness of the auxiliary member is less than a thickness of the upper solder ball. 
     
     
       20. The method of  claim 15 , wherein the auxiliary member comprises a Photo solder resist (PSR) or a metal.