Data storage element and manufacturing method thereof

Abstract

Disclosed herein, in some embodiments, is a memory device. The memory device includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. An upper surface of the bottom electrode faces away from the substrate. A bottom surface of the top electrode faces the substrate. A data storage layer is arranged between the bottom electrode and the top electrode. At least a portion of the bottom surface of the top electrode does not overlap with any portion of the top surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode. Furthermore, at least a portion of the top surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction.

The invention claimed is: 
     
       1. A method of manufacturing a memory device, the method comprising:
 forming a first conductive structure over a substrate; 
 forming a dielectric layer above the first conductive structure; 
 forming an opening in the dielectric layer that exposes an exposed portion of an upper surface of the first conductive structure; 
 forming a data storage layer above the exposed portion of the upper surface of the first conductive structure and within the opening, wherein a center of the data storage layer is displaced from a center of the upper surface of the first conductive structure in a first direction parallel to the upper surface of the first conductive structure; 
 forming a second conductive structure above the data storage layer and within the opening; and 
 performing a planarization process to remove a part of the data storage layer and the second conductive structure that are outside of the opening. 
 
     
     
       2. The method of  claim 1 , further comprising:
 forming a third conductive structure over the substrate and laterally separated from the first conductive structure by a lower dielectric layer; and 
 forming a fourth conductive structure over the third conductive structure, wherein the data storage layer vertically extends from the first conductive structure to a top of the fourth conductive structure. 
 
     
     
       3. The method of  claim 1 , wherein the first conductive structure is arranged in an etch stop layer and the opening exposes an upper surface of the etch stop layer. 
     
     
       4. The method of  claim 3 , wherein the opening extends below the upper surface of the first conductive structure into the etch stop layer. 
     
     
       5. The method of  claim 1 , wherein the data storage layer is deposited conformally on a bottom wall and sidewalls of the opening. 
     
     
       6. The method of  claim 1 , wherein a bottom surface of the second conductive structure has no overlap with the upper surface of the first conductive structure along the first direction. 
     
     
       7. The method of  claim 1 , wherein a sidewall of the second conductive structure is displaced from a sidewall of the first conductive structure in the first direction. 
     
     
       8. A method of manufacturing a memory device, the method comprising:
 forming a first conductive structure within a dielectric layer disposed over a substrate; 
 forming a data storage layer above an exposed portion of an upper surface of the first conductive structure, wherein the data storage layer laterally straddles an interface between an outermost sidewall of the first conductive structure and an inner sidewall of the dielectric layer, the data storage layer having a first outermost sidewall directly over the upper surface of the first conductive structure and an opposing second outermost sidewall laterally outside of the upper surface of the first conductive structure; and 
 forming a second conductive structure above the data storage layer. 
 
     
     
       9. The method of  claim 8 , wherein the data storage layer comprises a first lower surface directly over the first conductive structure and a second lower surface directly over the dielectric layer, the first lower surface being vertically above the second lower surface. 
     
     
       10. The method of  claim 8 , wherein the second conductive structure comprises a first lower surface and a second lower surface that are both directly over the data storage layer, the first lower surface being vertically above the second lower surface. 
     
     
       11. The method of  claim 8 , further comprising:
 an inter-level dielectric (ILD) layer laterally surrounding the first conductive structure, the ILD layer being vertically between the substrate and the dielectric layer. 
 
     
     
       12. The method of  claim 8 , wherein the data storage layer extends along opposing outermost sidewalls of the second conductive structure. 
     
     
       13. The method of  claim 8 , further comprising:
 forming a gate structure over the substrate, wherein the first conductive structure is disposed on a first side of the gate structure; 
 forming a third conductive structure along a second side of the gate structure; and 
 forming a fourth conductive structure directly contacting an upper surface of the third conductive structure. 
 
     
     
       14. The method of  claim 13 , further comprising:
 forming an inter-level dielectric (ILD) layer over the dielectric layer; 
 performing a first patterning process on the ILD layer to form a first opening that exposes the upper surface of the third conductive structure; 
 forming the fourth conductive structure within the first opening; 
 performing a second patterning process on the ILD layer to form a second opening after forming the fourth conductive structure; and 
 forming the data storage layer and the second conductive structure within the second opening. 
 
     
     
       15. The method of  claim 8 , wherein the data storage layer comprises a dielectric resistive memory layer. 
     
     
       16. The method of  claim 8 , wherein the first outermost sidewall of the data storage layer has a first length and the opposing second outermost sidewall of the data storage layer has a second length that is greater than the first length, as viewed in a cross-sectional view. 
     
     
       17. A method of manufacturing a memory device, the method comprising:
 forming a first conductive structure and a second conductive structure within a dielectric layer over a substrate; 
 forming an inter-level dielectric (ILD) layer over the dielectric layer; 
 performing a first patterning process on the ILD layer at a first time, wherein the first patterning process forms a first opening exposing an upper surface of the first conductive structure; 
 forming a third conductive structure within the first opening; 
 performing a second patterning process on the ILD layer at a second time that is different than the first time, wherein the second patterning process forms a second opening that exposes an upper surface and a sidewall of the second conductive structure; and 
 forming a data storage layer and an overlying fourth conductive structure within the second opening. 
 
     
     
       18. The method of  claim 17 , further comprising:
 forming a gate structure onto an upper surface of the substrate and laterally between a source region and a drain region; 
 forming the first conductive structure to physically contact the source region; and 
 forming the second conductive structure to physically contact the drain region. 
 
     
     
       19. The method of  claim 17 , wherein no more than 60% of a surface area of a bottom surface of the fourth conductive structure overlaps with a portion of the upper surface of the second conductive structure along a first direction. 
     
     
       20. The method of  claim 17 , wherein the second patterning process forms a sidewall and a horizontally extending surface of the dielectric layer.