Concentric staircase structure in three-dimensional memory device and method for forming the same

Abstract

Embodiments of 3D memory devices having a concentric staircase structure and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a concentric staircase structure in an intermediate of the memory array structure. The concentric staircase structure includes a plurality of concentric zones in a radial direction in a plan view. Each of the plurality of concentric zones includes a plurality of stairs in a tangential direction in the plan view.

What is claimed is: 
     
       1. A three-dimensional (3D) memory device, comprising:
 a memory array structure; and 
 a concentric staircase structure in an intermediate of the memory array structure, wherein the concentric staircase structure comprises:
 a plurality of stairs at different depths, 
 a plurality of concentric zones in a radial direction in a plan view, and each of the plurality of concentric zones is a respective concentric ring with respect to a common center of the concentric staircase structure, and comprises a corresponding subset of stairs in a tangential direction in the plan view, and 
 a plurality of sectors in the tangential direction, and each of the plurality of sectors is defined between two adjacent radial lines from the common center of the concentric staircase structure that form boundaries of the stairs, and comprises a corresponding subset of stairs in the radial direction in the plan view, 
 wherein each of the plurality stairs is an overlap between one corresponding concentric zone and one corresponding sector. 
 
 
     
     
       2. The 3D memory device of  claim 1 , wherein the plurality of stairs in each of the plurality of concentric zones have a nominally same lateral dimension. 
     
     
       3. The 3D memory device of  claim 1 , wherein the plurality of concentric zones are at different depths. 
     
     
       4. The 3D memory device of  claim 1 , wherein the plurality corresponding subset of stairs in each of the plurality of sectors have different lateral dimensions. 
     
     
       5. The 3D memory device of  claim 1 , wherein the plurality of sectors are at different depths. 
     
     
       6. The 3D memory device of  claim 1 , wherein the concentric staircase structure has a concentric circles layout. 
     
     
       7. The 3D memory device of  claim 1 , wherein the memory array structure comprises vertically interleaved conductive layers and dielectric layers, and a height of each stair is equal to a total thickness of one or more pairs of the conductive layers and dielectric layers. 
     
     
       8. The 3D memory device of  claim 1 , wherein a bottom stair of a higher concentric zone is higher than a top stair of a lower concentric zone in every pair of adjacent concentric zones. 
     
     
       9. The 3D memory device of  claim 1 , wherein a bottom stair of a higher sector is higher than a top stair of a lower sector in every pair of adjacent sectors. 
     
     
       10. The 3D memory device of  claim 1 , wherein an angle between two adjacent radial lines is equal to or less than  90  degrees. 
     
     
       11. A method for forming a concentric staircase structure of a three-dimensional (3D) memory device, comprising:
 forming a plurality of sectors in a tangential direction in a plan view in an intermediate of a dielectric stack comprising vertically interleaved sacrificial layers and dielectric layers, wherein each of the plurality of sectors is at different depths; and 
 in each of the plurality of sectors, forming a plurality of stairs towards a center of the plurality of sectors in a radial direction in the plan view, such that each stair of the plurality of sectors are at different depths; 
 wherein forming the plurality of sectors comprises simultaneously forming each pair of symmetric sectors with respect to the center of the sectors. 
 
     
     
       12. The method of  claim 11 , wherein forming the plurality of sectors comprises:
 sequentially forming a plurality of subsets of the plurality of sectors, each subset of the plurality of sectors being at a same depth; and 
 chopping at least some of the plurality of sectors, such that each sector is at different depths. 
 
     
     
       13. The method of  claim 12 , wherein sequentially forming the plurality of subsets of the plurality of sectors comprises:
 patterning a first sector mask comprising a first opening for a first subset of the plurality of subsets of the sectors; 
 etching one or more pairs of the sacrificial layers and dielectric layers through the first sector mask; 
 patterning a second sector mask comprising a second opening for a second subset and the first subset of the plurality of subsets of the sectors; and 
 etching one or more pairs of the sacrificial layers and dielectric layers through the second sector mask. 
 
     
     
       14. The method of  claim 13 , wherein chopping the at least some of the plurality of sectors comprises:
 patterning a chop mask comprising an opening of the at least some of the plurality of sectors; and 
 etching a plurality of pairs of the sacrificial layers and dielectric layers through the chop mask. 
 
     
     
       15. The method of  claim 11 , wherein forming the plurality of stairs in each of the plurality of sectors comprises:
 patterning a trim-etch mask comprising an opening of part of the plurality of sectors; and 
 performing a plurality of trim-etch cycles through the trim-etch mask towards the center of the plurality of sectors in the radial direction. 
 
     
     
       16. The method of  claim 15 , wherein a concentric zone comprising a plurality of stairs in a tangential direction in the plan view is formed by each of the plurality of trim-etch cycles. 
     
     
       17. The method of  claim 11 , further comprising:
 after forming the plurality of stairs in each of the plurality of sectors, forming a memory stack comprising vertically interleaved conductive layers and the dielectric layers by replacing the sacrificial layers of the dielectric stack with the conductive layers.