Systems and methods for staggering read operation of sub-blocks

Abstract

A memory device with one or more planes having sub-blocks is disclosed. The memory device may further include a voltage switch transistor for each of sub-blocks. Additionally, the memory device may further include a row decoder for each of sub-blocks. As a result, an operation to two sub-blocks can be performed at different times. For example, using a row decoder and voltage switch transistor, a sub-block can be initially read, followed by a subsequent read of another sub-block using a separate row decoder and voltage switch transistor. By staggering the read operations through a time delay, the peak current Icc associated with the supply voltage can be reduced.

What is claimed is: 
     
       1. A method for optimizing an operation of a memory device, the method comprising the steps of:
 accessing, by a first row decoder coupled to a first sub-block of a first memory block, the first sub-block of the first memory block at a first time; and 
 accessing, by a second row decoder separate from the first row decoder and coupled to a second sub-block of the first memory block, the second sub-block of the first memory block at a second time that is different from the first time, 
 wherein the second time defines a time delay that is chronologically after the first time, and 
 wherein the time delay is determined based upon a word line voltage ramp rate control. 
 
     
     
       2. The method according to  claim 1 , wherein:
 accessing the first sub-block comprises reading the first sub-block at the first time; and 
 accessing the second sub-block comprises reading the second sub-block at the second time. 
 
     
     
       3. The method according to  claim 1 , wherein accessing the first sub-block comprises providing, by the first row decoder, voltage to a first switch transistor. 
     
     
       4. The method according to  claim 1 , wherein the first sub-block is located on a first plane, and the second sub-block is located on a second plane. 
     
     
       5. The method according to  claim 1 , further comprising the step of providing, by a voltage switch transistor, voltage to the first row decoder and the second row decoder. 
     
     
       6. A memory system, comprising:
 a memory device; 
 a first row decoder coupled to a first sub-block of a first memory block; 
 a second row decoder, separate from the first row decoder, coupled to a second sub-block of the first memory block; and 
 a controller operatively coupled to the memory device, the controller being configured to:
 access, by the first row decoder, the first sub-block of the first memory block at a first time; and 
 access, by the second row decoder, the second sub-block of the first memory block at a second different from the first time, 
 
 wherein the second time defines a time delay that is chronologically after the first time, and 
 wherein the time delay is determined based upon a word line voltage ramp rate control. 
 
     
     
       7. The memory system according to  claim 6 , wherein the controller is further configured to:
 read the first sub-block at the first time; and 
 read the second sub-block at the second time. 
 
     
     
       8. The memory system according to  claim 6 , wherein the controller is further configured to provide, using the first row decoder, voltage to a first switch transistor. 
     
     
       9. The memory system according to  claim 6 , wherein the first sub-block is located on a first plane, and the second sub-block is located on a second plane. 
     
     
       10. The memory system according to  claim 6 , wherein the controller is further configured to provide, using a voltage switch transistor, voltage to the first row decoder and the second row decoder. 
     
     
       11. A non-transitory computer readable storage medium configured to store instructions that, when executed by a processor includes a controller of a memory system, cause the memory system to carry out steps to:
 access, by a first row decoder coupled to a first sub-block of a first memory block, the first sub-block of the first memory block at a first time; and 
 access, by a second row decoder separate from the first row decoder and coupled to a second sub-block of the first memory block, the second sub-block of the first memory block at a second different from the first time, 
 wherein the second time defines a time delay that is chronologically after the first time, and 
 wherein the time delay is determined based upon a word line voltage ramp rate control. 
 
     
     
       12. The non-transitory computer readable storage medium according to  claim 11 , wherein the controller is further configured to:
 read the first sub-block at the first time; and 
 read the second sub-block comprises reading the second sub-block at the second time. 
 
     
     
       13. The non-transitory computer readable storage medium according to  claim 11 , wherein the controller is further configured to provide, using the first row decoder, voltage to a first switch transistor. 
     
     
       14. The non-transitory computer readable storage medium according to  claim 11 , wherein the first sub-block is located on a first plane, and the second sub-block is located on a second plane.