Semiconductor devices and methods of manufacturing thereof

Abstract

A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a plurality of semiconductor layers vertically separated from one another, wherein each of the plurality of semiconductor layers extends along a first lateral direction; and 
 a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers; 
 wherein the lower portion of the gate structure includes:
 a plurality of first gate sections, each of the first gate sections having a first curvature-based profile when viewed from its cross-section expanding over the first and second lateral directions; and 
 a plurality of second gate sections, each of the second gate sections having a second, different curvature-based profile when viewed from its cross-section expanding over the first and second lateral directions. 
 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the first curvature-based profile has a single arc, and the second curvature-based profile has a plurality of arcs connected to each other. 
     
     
       3. The semiconductor device of  claim 2 , wherein each of the plurality of semiconductor layers has sidewalls extending along the first direction, and wherein an angle between a portion of each of the sidewalls that is wrapped by a corresponding one of the plurality of first gate sections and the single arc is less than 90 degrees. 
     
     
       4. The semiconductor device of  claim 3 , wherein the sidewalls of each of the plurality of semiconductor layers and the corresponding first gate section are in direct contact with each other. 
     
     
       5. The semiconductor device of  claim 3 , further comprising a connected layer disposed between the sidewalls of each of the plurality of semiconductor layers and the corresponding first gate section, wherein the connecter layer includes a material that has an etching selectivity with respect to a material of the plurality of semiconductor layers. 
     
     
       6. The semiconductor device of  claim 5 , wherein the connecter layer includes a material selected from the group consisting of: SiGeO, SiO, SiGeN, SiN, SiGeS, and SiS. 
     
     
       7. The semiconductor device of  claim 2 , wherein the plurality of arcs of the second curvature-based profile each curve inwardly toward the plurality of second gate sections. 
     
     
       8. The semiconductor device of  claim 2 , wherein each of the plurality of semiconductor layers has sidewalls extending along the first direction, and wherein an angle between a projection of each of the sidewalls and any one of the plurality of arcs of the second curvature-based profile is less than 90 degrees. 
     
     
       9. The semiconductor device of  claim 1 , wherein each of the plurality of second gate sections is vertically disposed between adjacent ones of the plurality of semiconductor layers, and wherein each of the plurality of second gate sections has ends that each extend along the second lateral direction. 
     
     
       10. A semiconductor device, comprising:
 a plurality of semiconductor layers vertically separated from one another, wherein each of the plurality of semiconductor layers extends along a first lateral direction; 
 a gate structure that extends along a second lateral direction, wherein the gate structure comprises a plurality of first gate sections and a plurality of second gate sections, and wherein the plurality of first gate sections are laterally aligned with the plurality of semiconductor layers, respectively, and the plurality of second gate sections are each vertically disposed between adjacent ones of the plurality of semiconductor layers; and 
 an inner spacer comprising a first group and a second group; 
 wherein each of the first group of the inner spacer contacts a first end of a corresponding one of the plurality of first gate sections, and each of the second group of the inner spacer contacts a second end of a corresponding one of the plurality of second gate sections; and 
 wherein the first end has a single arc, and the second end has a plurality of arcs connected to one another. 
 
     
     
       11. The semiconductor device of  claim 10 , wherein each of the plurality of semiconductor layers has sidewalls extending along the first direction, and wherein an angle between a portion of each of the sidewalls that is wrapped by a corresponding one of the plurality of first gate sections and the single arc is less than 90 degrees. 
     
     
       12. The semiconductor device of  claim 10 , wherein each of the plurality of semiconductor layers has sidewalls extending along the first direction, and wherein an angle between a projection of each of the sidewalls and any one of the plurality of arcs is less than 90 degrees. 
     
     
       13. The semiconductor device of  claim 10 , wherein the single arc curves inwardly toward a corresponding one of the plurality of first gate sections. 
     
     
       14. The semiconductor device of  claim 10 , wherein the plurality of arcs each curve inwardly toward a corresponding one of the plurality of second gate sections. 
     
     
       15. The semiconductor device of  claim 10 , wherein each of the plurality of semiconductor layers has sidewalls extending along the first direction, the semiconductor device further comprising a connected layer disposed between the sidewalls of the plurality of semiconductor layers and the plurality of first gate sections. 
     
     
       16. The semiconductor device of  claim 15 , wherein the connecter layer includes a material that has an etching selectivity with respect to a material of the plurality of semiconductor layers. 
     
     
       17. The semiconductor device of  claim 15 , wherein the connecter layer includes a material selected from the group consisting of: SiGeO, SiO, SiGeN, SiN, SiGeS, and SiS. 
     
     
       18. The semiconductor device of  claim 10 , wherein each of the plurality of semiconductor layers has sidewalls extending along the first direction, and wherein the sidewalls of the plurality of semiconductor layers are in direct contact with the plurality of first gate sections. 
     
     
       19. A semiconductor device, comprising:
 a plurality of semiconductor layers vertically separated from one another, each of the plurality of semiconductor layers extending along a first lateral direction between a first source/drain structure and a second source/drain structure; 
 a gate structure extending along a second lateral direction and comprising at least a lower portion that wraps around each of the plurality of semiconductor layers; and 
 an inner spacer disposed between the lower portion of the gate structure and the first or second source/drain structure, and comprising a first group and a second group; 
 wherein each of the first group of the inner spacer contacts a first end of a corresponding one of the plurality of first gate sections, and each of the second group of the inner spacer contacts a second end of a corresponding one of the plurality of second gate sections; and 
 wherein the first end has a single arc, and the second end has a plurality of arcs connected to one another. 
 
     
     
       20. The semiconductor device of  claim 19 , wherein each of the plurality of semiconductor layers has sidewalls extending along the first direction, wherein a first angle between a portion of each of the sidewalls that is wrapped by a corresponding one of the plurality of first gate sections and the single arc is less than 90 degrees, and wherein a second angle between a projection of each of the sidewalls and any one of the plurality of arcs is less than 90 degrees.