Integrated circuit semiconductor device including through silicon via

Abstract

An integrated circuit semiconductor device includes a substrate including a first surface and a second surface opposite the first surface, a trench in the substrate, the trench extending from the first surface of the substrate toward the second surface of the substrate, a through silicon via (TSV) landing part in the trench, the TSV landing part having a first portion spaced apart from the first surface of the substrate, and a second portion between the first portion and the first surface of the substrate, the first portion being wider than the second portion, a TSV hole in the substrate, the TSV hole extending from the second surface of the substrate and aligned with a bottom surface of the TSV landing part, and a TSV in the TSV hole and in contact with the bottom surface of the TSV landing part.

What is claimed is: 
     
       1. An integrated circuit semiconductor device, comprising:
 a substrate including a first surface and a second surface opposite the first surface; 
 a trench in the substrate, the trench extending from the first surface of the substrate toward the second surface of the substrate; 
 a through silicon via (TSV) landing part in the trench, the TSV landing part having:
 a first portion spaced apart from the first surface of the substrate, and 
 a second portion between the first portion and the first surface of the substrate, the first portion being wider than the second portion; 
 
 a TSV hole in the substrate, the TSV hole extending from the second surface of the substrate and aligned with a bottom surface of the TSV landing part; and 
 a TSV in the TSV hole and in contact with the bottom surface of the TSV landing part wherein a width of the TSV increases and does not decrease in a direction from the first surface to the second surface. 
 
     
     
       2. The integrated circuit semiconductor device as claimed in  claim 1 , wherein the first surface is a front surface of the substrate, and the second surface is a rear surface of the substrate. 
     
     
       3. The integrated circuit semiconductor device as claimed in  claim 1 , wherein:
 the trench includes upper and lower trenches in communication with each other, 
 the second portion of the TSV landing part is an upper TSV landing part buried in the upper trench adjacent to the first surface of the substrate, and 
 the first portion of the TSV landing part is a lower TSV landing part buried in the lower trench, the lower trench being between the upper trench and the second surface of the substrate. 
 
     
     
       4. The integrated circuit semiconductor device as claimed in  claim 3 , wherein a width of at least a portion of the lower TSV landing part is greater than a width of a portion of the upper TSV landing part. 
     
     
       5. The integrated circuit semiconductor device as claimed in  claim 3 , wherein a cross-sectional shape of the lower TSV landing part is one of a circular shape, a semicircular shape, and a polygonal shape. 
     
     
       6. The integrated circuit semiconductor device as claimed in  claim 1 , wherein the trench has a first depth from the first surface, the TSV hole has a second depth from the second surface, and the second depth is greater than the first depth. 
     
     
       7. The integrated circuit semiconductor device as claimed in  claim 1 , wherein the TSV landing part includes a first TSV landing part and a second TSV landing part spaced apart from each other, a cross-sectional shape of the first TSV landing part being different from a cross-sectional shape of the second TSV landing part. 
     
     
       8. The integrated circuit semiconductor device as claimed in  claim 1 , wherein a width of a first portion of the TSV adjacent to the second surface is greater than a width of a second portion of the TSV adjacent to the TSV landing part. 
     
     
       9. The integrated circuit semiconductor device as claimed in  claim 1 , further comprising a trench liner layer and a via hole liner layer on inner sidewalls of the trench and the TSV hole, respectively. 
     
     
       10. An integrated circuit semiconductor device, comprising:
 a substrate including a first surface and a second surface opposite the first surface; 
 active elements on the first surface of the substrate; 
 through silicon via (TSV) landing parts connected to the active elements, the TSV landing parts being buried in respective trenches within the substrate, and each of the TSV landing parts having:
 a first portion spaced apart from the first surface of the substrate, and 
 a second portion between the first portion and the first surface of the substrate, the first portion being wider than the second portion; 
 
 TSV holes in the substrate, the TSV holes extending from the second surface of the substrate and being aligned with bottom surface of the TSV landing parts; and 
 TSVs connected to the TSV landing parts, respectively, the TSVs being buried in the TSV holes, respectively, wherein some of the TSV landing parts are connected to a power rail part or a ground rail part, wherein a width of each TSV of the TSVs increases and does not decrease in a direction from the first surface to the second surface. 
 
     
     
       11. The integrated circuit semiconductor device as claimed in  claim 10 , wherein:
 each of the respective trenches includes an upper trench extending to a certain depth from the first surface and a lower trench extending from the upper trench toward the second surface, and 
 the TSV landing parts are buried in the upper and lower trenches. 
 
     
     
       12. The integrated circuit semiconductor device as claimed in  claim 10 , further comprising a local wiring layer on the first surface of the substrate, the local wiring layer including a local wiring connected to the TSV landing parts, and the TSV landing parts being connected to source and drain regions of the active elements through the local wiring. 
     
     
       13. The integrated circuit semiconductor device as claimed in  claim 12 , further comprising an upper multilayer wiring layer on the local wiring layer. 
     
     
       14. The integrated circuit semiconductor device as claimed in  claim 10 , further comprising:
 a lower multilayer wiring layer on the second surface of the substrate; and 
 a power and ground terminal on the lower multilayer wiring layer and connected to the TSV landing parts, the power and ground terminal being connected to the power rail part or the ground rail part via the lower multilayer wiring layer and the TSVs. 
 
     
     
       15. The integrated circuit semiconductor device as claimed in  claim 10 , further comprising:
 a lower multilayer wiring layer on the second surface of the substrate; and 
 a signal input/output (I/O) terminal on the lower multilayer wiring layer and connected to the TSV landing parts, the signal input/output (I/O) terminal being connected to the power rail part or the ground rail part via the lower multilayer wiring layer and the TSVs. 
 
     
     
       16. The integrated circuit semiconductor device as claimed in  claim 10 , further comprising:
 an upper multilayer wiring layer on the first surface of the substrate; 
 a lower multilayer wiring layer on the second surface of the substrate; 
 an additional TSV in the substrate; and 
 a signal input/output (I/O) terminal on the lower multilayer wiring layer and connected to the active elements through the upper multilayer wiring layer via the lower multilayer wiring layer and the additional TSV. 
 
     
     
       17. An integrated circuit semiconductor device, comprising:
 a substrate including a first surface and a second surface opposite the first surface; 
 active elements on the first surface of the substrate, the active elements including:
 finFET transistors with pins on the first surface of the substrate, the pins extending in a first direction, 
 gate electrodes extending in a second direction vertical to the first direction, and 
 source and drain regions at opposite sides of each of the gate electrodes; 
 
 through silicon via (TSV) landing parts connected to the source drain regions of the finFET transistors and buried in the substrate, each of the TSV landing parts having:
 a first portion spaced apart from the first surface of the substrate, and 
 a second portion between the first portion and the first surface of the substrate, the first portion being wider than the second portion; and 
 
 TSVs connected to the TSV landing parts and buried in TSV holes aligned with bottom surfaces of the TSV landing parts from the second surface, 
 wherein a width of each TSV of the TSVs increases and does not decrease in a direction from the first surface to the second surface, 
 wherein some of the TSV landing parts are connected to a power rail part or a ground rail part in a same direction as the first direction. 
 
     
     
       18. The integrated circuit semiconductor device as claimed in  claim 17 , further comprising a signal input/output (I/O) terminal electrically connected to some of the TSV landing parts. 
     
     
       19. The integrated circuit semiconductor device as claimed in  claim 17 , wherein:
 the first surface is a front surface of the substrate, 
 the second surface is a rear surface of the substrate, 
 a preliminary substrate is further attached on the first surface, and 
 a power and ground terminal connected to a lower multilayer wiring layer is further positioned on the second surface. 
 
     
     
       20. The integrated circuit semiconductor device as claimed in  claim 17 , wherein each of the TSV landing parts has a certain depth from the first surface, and a cross-sectional shape of each of the TSV landing parts is one of a circular shape, a semicircular shape, and a polygonal shape.