Structure and process of integrated circuit having latch-up suppression

Abstract

A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

What is claimed is: 
     
       1. A method of forming an integrated circuit, the method comprising:
 forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate; 
 form a first fin active region extruded from the N-well and a second fin active region extruded from the P-well; 
 forming a first isolation feature inserted between and vertically extending through the N-well and the P-well; and 
 forming a second isolation feature overlying the N-well and the P-well and laterally disposed between the first and the second fin active regions. 
 
     
     
       2. The method of  claim 1 , further comprising forming a third isolation feature on the N-well and the P-well and laterally contacting the first and the second fin active regions. 
     
     
       3. The method of  claim 2 , wherein the first isolation feature is free of contact with the first and second fin active regions. 
     
     
       4. The method of  claim 2 , wherein the second isolation feature is vertically aligned with the first isolation feature. 
     
     
       5. The method of  claim 2 , wherein the P-well is a first P-well disposed along a first sidewall of the N-well, the method further includes
 forming a second P-well disposed along a second sidewall of the N-well; and 
 forming a fourth isolation feature inserted between and vertically extending through the second P-well and the N-well, wherein the fourth isolation feature is disposed between the first fin active region and a third fin active region. 
 
     
     
       6. The method of  claim 5 , further comprising forming a first gate and a second gate disposed on a first side and a second side of the second isolation feature. 
     
     
       7. The method of  claim 6 , wherein the second isolation feature has a bottom surface below a top surface of the third isolation feature, and wherein the second isolation feature has a top surface co-planar with top surfaces of the first gate and the second gate. 
     
     
       8. The method of  claim 2 , wherein the second isolation feature extends into the third isolation feature. 
     
     
       9. The method of  claim 2 , wherein the second isolation feature is narrower than the third isolation feature. 
     
     
       10. A semiconductor structure, comprising:
 a semiconductor substrate; 
 a deep trench isolation feature extending into the semiconductor substrate; 
 a n-type doped well (N-well) disposed in the semiconductor substrate and along a first sidewall of the deep trench isolation feature; and 
 a p-type doped well (P-well) disposed in the semiconductor substrate adjacent to the N-well and along a second sidewall of the deep trench isolation feature, wherein a bottom surface of the deep trench isolation feature is below bottom surfaces of the N-well and the P-well. 
 
     
     
       11. The semiconductor structure of  claim 10 , further comprising:
 a shallow trench isolation feature disposed over and directly contact top surfaces of the N-well, the P-well and the deep trench isolation feature; and 
 a gate-cut feature extending into the shallow trench isolation feature. 
 
     
     
       12. The semiconductor structure of  claim 11 , further comprising a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, wherein the shallow trench isolation feature laterally contacts a sidewall of the first fin active region and a sidewall of the second fin active region. 
     
     
       13. The semiconductor structure of  claim 12 , wherein the deep trench isolation feature is free of contact with the first fin and the second fin. 
     
     
       14. The semiconductor structure of  claim 12 , wherein the gate-cut feature is vertically aligned with the deep trench isolation feature and is interposed between the first and second fin active regions. 
     
     
       15. The semiconductor structure of  claim 11 , wherein the top surfaces of the N-well, the P-well and the deep trench isolation feature are coplanar. 
     
     
       16. The semiconductor structure of  claim 11 , further comprising a first gate and a second gate disposed on a first side and a second side of the gate-cut feature, wherein the gate-cut feature has a bottom surface below a top surface of the shallow trench isolation feature, and wherein the gate-cut feature has a top surface co-planar with top surfaces of the first gate and the second gate. 
     
     
       17. The semiconductor structure of  claim 10 , wherein a portion of the deep trench isolation feature extended into the semiconductor substrate has a height about 0.2 to about 0.5 of a length of the deep trench isolation feature. 
     
     
       18. A method of forming an integrated circuit, the method comprising:
 receiving a design layout of the integrated circuit having an inverter that includes a n-type field effect transistor and a p-type field effect transistor sharing a gate; 
 modifying the design layout such that the gate of the inverter has an end aligned to a common edge of a n-type doped well (N-well) and a p-type doped well (P-well); and 
 fabricating the integrated circuit according to the modified design layout, wherein fabricating of the integrated circuit includes: 
 forming the N-well and P-well in a semiconductor substrate; 
 forming a deep trench isolation feature extending through the common edge of the N-well and P-well; 
 forming the gate over the N-well and the P-well; and 
 forming a gate-cut feature extends through the gate such that the gate-cut feature is vertically aligned with the common edge of the N-well and P-well. 
 
     
     
       19. The method of  claim 18 , wherein the fabricating of the integrated circuit further includes:
 forming a first fin active region extruded from the N-well; 
 forming a second fin active region extruded from the P-well; and 
 forming a shallow trench isolation feature on the semiconductor substrate such that a bottom surface of the shallow trench isolation feature contacts top surfaces of the N-well and P-well and a top surface of the deep trench isolation feature. 
 
     
     
       20. The method of  claim 19 , wherein
 the forming a gate-cut feature includes forming the gate-cut feature extending into the shallow trench isolation feature; and 
 the forming a deep trench isolation feature includes forming the deep trench isolation such that top surfaces of the N-well and P-well and a top surface of the deep trench isolation feature are coplanar.