Semiconductor memory device having contact plugs extend in the stacking direction of the plurality of the first and second conductive layers

Abstract

A semiconductor memory device including: plural first conductive layers stacked on a substrate; plural second conductive layers each stacked between the first conductive layers; a pillar that extends in a stacking direction of the first and second conductive layers and forms plural memory cells at intersections of the first and second conductive layers in a region where first and second conductive layers are arranged; a first contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the first conductive layers in the region where the first and second conductive layers are arranged; and a second contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the second conductive layers in the region where the first conductive layers and second conductive layers are arranged.

The invention claimed is: 
     
       1. A semiconductor memory device comprising:
 a plurality of first conductive layers stacked on a substrate; 
 a plurality of second conductive layers each stacked between the first conductive layers; 
 a pillar that extends in a stacking direction of the plurality of first conductive layers and the plurality of second conductive layers and forms a plurality of memory cells at intersections of the plurality of first conductive layers and the plurality of second conductive layers in a region where the plurality of first conductive layers and the plurality of second conductive layers are arranged; 
 a first contact plug that extends in the stacking direction of the plurality of first conductive layers and the plurality of second conductive layers and is connected to the plurality of first conductive layers in the region where the plurality of first conductive layers and the plurality of second conductive layers are arranged; and 
 a second contact plug that extends in the stacking direction of the plurality of first conductive layers and the plurality of second conductive layers and is connected to the plurality of second conductive layers in the region where the plurality of first conductive layers and the plurality of second conductive layers are arranged. 
 
     
     
       2. The semiconductor memory device according to  claim 1 , wherein
 the plurality of first conductive layers are (3n+1)th conductive layers (n is an integer of 0 or more) when counted from a substrate side, and 
 the plurality of second conductive layers are (3n+2)th conductive layers when counted from the substrate side. 
 
     
     
       3. The semiconductor memory device according to  claim 1 , wherein
 the plurality of first conductive layers are (4n+1)th conductive layers (n is an integer of 0 or more) when counted from a substrate side, and 
 the plurality of second conductive layers are (4n+2)th conductive layers when counted from the substrate side. 
 
     
     
       4. The semiconductor memory device according to  claim 1 , wherein
 the plurality of first conductive layers are connected to the first contact plug via a first protrusion having a first distance from a side surface of the first contact plug, and 
 the plurality of second conductive layers are connected to the second contact plug via a second protrusion having a second distance larger than the first distance from a side surface of the second contact plug. 
 
     
     
       5. The semiconductor memory device according to  claim 1 , wherein
 the first contact plug has a first diameter at a first height and the second contact plug has a second diameter larger than the first diameter at the first height, and 
 the plurality of first conductive layers are in contact with a side surface of the first contact plug and the plurality of second conductive layers are in contact with a side surface of the second contact plug.