Coreless architecture and processing strategy for EMIB-based substrates with high accuracy and high density

Abstract

Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes a plurality of conductive layers over a package substrate. The conductive layers include a first conductive layer and first-level interconnects (FLIs) in the package substrate. The semiconductor package also includes a solder resist that surrounds the FLIs, where the solder resist has a top surface that is substantially coplanar to top surfaces of the FLIs, a bridge coupled directly to the first conductive layer with solder balls, where the first conductive layer is coupled to the FLIs, and a dielectric over the conductive layers, the bridge, and the solder resist of the package substrate. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first conductive layer may include first conductive pads and second conductive pads. The FLIs may include first conductive vias, second conductive vias, diffusion layers, and third conductive pads.

What is claimed is: 
     
       1. A semiconductor package, comprising:
 a plurality of conductive layers over a package substrate, wherein the plurality of conductive layers include a first conductive layer and first-level interconnects (FLIs) in the package substrate; 
 a solder resist surrounding the FLIs, wherein the solder resist has a top surface that is substantially coplanar to a plurality of top surfaces of the FLIs; 
 a bridge having a top with conductive pads, the conductive pads coupled directly to the first conductive layer with a plurality of solder balls, the bridge in a cavity in the package substrate, and the bridge having sidewalls, wherein the first conductive layer is coupled to the FLIs; 
 an encapsulation layer laterally surrounding the bridge in the cavity, the encapsulation layer on the top of the bridge and in contact with the conductive pads of the bridge, the encapsulation layer along less than an entirety of the sidewalls of the bridge, and the encapsulation layer having a bottommost surface above a bottommost surface of the bridge; and 
 a dielectric over the plurality of conductive layers, the bridge, and the solder resist of the package substrate. 
 
     
     
       2. The semiconductor package of  claim 1 , wherein the bridge is an embedded multi-die interconnect bridge (EMIB). 
     
     
       3. The semiconductor package of  claim 1 , wherein the first conductive layer includes a plurality of first conductive pads and a plurality of second conductive pads, and wherein the FLIs include a plurality of first conductive vias, a plurality of second conductive vias, a plurality of diffusion layers, and a plurality of third conductive pads. 
     
     
       4. The semiconductor package of  claim 3 , wherein the plurality of first conductive pads are coupled to the plurality of third conductive pads with the plurality of first conductive vias and diffusion layers, wherein the plurality of second conductive pads are coupled to the plurality of third conductive pads with the plurality of second conductive vias and diffusion layers, wherein the plurality of diffusion layers are between the plurality of third conductive pads and the plurality of first and second conductive vias, wherein the plurality of first and second conductive vias have top surfaces and bottom surfaces that are opposite to the top surfaces, and wherein the top surfaces of the plurality of first and second conductive vias are coupled directly to the plurality of diffusion layers. 
     
     
       5. The semiconductor package of  claim 4 , wherein the top surfaces of the plurality of first and second vias have a width that is less than a width of the bottom surfaces of the plurality of first and second vias. 
     
     
       6. The semiconductor package of  claim 3 , wherein the plurality of top surfaces of the FLIs are top surfaces of the plurality of third conductive pads, and wherein the plurality of first and second conductive pads are on the solder resist. 
     
     
       7. The semiconductor package of  claim 3 , further comprising:
 a conductive ring layer on the solder resist, wherein the conductive ring layer surrounds the plurality of first conductive pads; 
 a plurality of conductive pads on a bottom surface of the bridge, wherein the bottom surface of the bridge is opposite to a top surface of the bridge, and wherein the plurality of conductive pads of the bridge are coupled directly to the plurality of first conductive pads of the first conductive layer with the plurality of solder bumps; and 
 an encapsulation layer surrounds the plurality of first conductive pads, the plurality of solder bumps, a portion of the conductive ring layer, and a portion of the bridge. 
 
     
     
       8. The semiconductor package of  claim 7 , wherein the plurality of first conductive vias have a thickness that is substantially equal to a thickness of the plurality of second conductive vias, wherein the conductive ring layer has a thickness that is substantially equal to a thickness of the plurality of first and second conductive pads, and wherein the plurality of first conductive pads have a width that is less than a width of the plurality of second conductive pads. 
     
     
       9. The semiconductor package of  claim 7 , wherein the dielectric is between and surrounds the top surface of the bridge and a third conductive layer of the plurality of conductive layers, wherein the conductive ring layer includes one or more conductive materials, wherein the one or more conductive materials include copper, zinc oxide, ferric oxide, or copper oxide, wherein the bridge is coupled to a power source with a through silicon via (TSV) or a conductive layer of the FLIs when the conductive ring layer is a copper ring layer, wherein the conductive layer of the FLIs is on and coupled to one or more of the plurality of first vias, and wherein the TSV couples the third conductive layer to the plurality of conductive pads of the bridge. 
     
     
       10. A semiconductor package, comprising:
 a plurality of conductive layers over a package substrate, wherein the plurality of conductive layers include a first conductive layer and FLIs in the package substrate; 
 a plurality of conductive pillars coupled to the first conductive layer and the FLIs, wherein the first conductive layer is coupled to the FLIs; 
 a solder resist surrounding the FLIs, wherein the solder resist has a top surface that is substantially coplanar to a plurality of top surfaces of the FLIs; 
 a bridge having a top with conductive pads, the conductive pads coupled directly to the first conductive layer with a plurality of solder balls, the bridge in a cavity in the package substrate, and the bridge having sidewalls; 
 an encapsulation layer laterally surrounding the bridge in the cavity, the encapsulation layer on the top of the bridge and in contact with the conductive pads of the bridge, the encapsulation layer along less than an entirety of the sidewalls of the bridge, and the encapsulation layer having a bottommost surface above a bottommost surface of the bridge; 
 a dielectric over the plurality of conductive layers, the plurality of conductive pillars, the bridge, and the solder resist of the package substrate; and 
 a plurality of dies over the package substrate, wherein the plurality of dies are coupled directly to the FLIs with a plurality of conductive bumps, and wherein the plurality of dies are communicatively coupled with the bridge. 
 
     
     
       11. The semiconductor package of  claim 10 , wherein the bridge is an EMIB, and wherein the first conductive layer includes a plurality of first conductive pads and a plurality of second conductive pads, and wherein the FLIs include a plurality of first conductive vias, a plurality of second conductive vias, and a plurality of diffusion layers. 
     
     
       12. The semiconductor package of  claim 11 , wherein the plurality of first conductive pads are coupled to the plurality of diffusion layers with the plurality of first conductive vias, wherein the plurality of second conductive pads are coupled to the plurality of diffusion layers with the plurality of second conductive vias, wherein the plurality of diffusion layers are between the plurality of conductive bumps and the plurality of first and second conductive vias, wherein the plurality of first and second conductive vias have top surfaces and bottom surfaces that are opposite to the top surfaces, and wherein the top surfaces of the plurality of first and second conductive vias are coupled directly to the plurality of diffusion layers. 
     
     
       13. The semiconductor package of  claim 12 , wherein the top surfaces of the plurality of first and second vias have a width that is less than a width of the bottom surfaces of the plurality of first and second vias. 
     
     
       14. The semiconductor package of  claim 11 , wherein the plurality of top surfaces of the FLIs are top surfaces of the plurality of diffusion layers, wherein the plurality of first and second conductive pads are on the solder resist, and wherein the plurality of diffusion layers are coupled directly to the plurality of conductive bumps and the plurality of first and second conductive vias. 
     
     
       15. The semiconductor package of  claim 11 , further comprising:
 a conductive ring layer on the solder resist, wherein the conductive ring layer surrounds the plurality of first conductive pads; 
 a plurality of third conductive pads on a bottom surface of the bridge, and a plurality of fourth conductive pads on a top surface of the bridge, wherein the bottom surface of the bridge is opposite to the top surface of the bridge, and wherein the plurality of third conductive pads of the bridge are coupled directly to the plurality of first conductive pads of the first conductive layer with the plurality of solder bumps; 
 a first encapsulation layer surrounds the plurality of first conductive pads, the plurality of solder bumps, a portion of the conductive ring layer, and a portion of the bridge; and 
 a second encapsulation layer over the plurality of dies and the package substrate, wherein the second encapsulation layer surrounds the conductive bumps. 
 
     
     
       16. The semiconductor package of  claim 15 , wherein the plurality of first conductive vias have a thickness that is substantially equal to a thickness of the plurality of second conductive vias, wherein the conductive ring layer has a thickness that is substantially equal to a thickness of the plurality of first and second conductive pads, and wherein the plurality of first conductive pads have a width that is less than a width of the plurality of second conductive pads. 
     
     
       17. The semiconductor package of  claim 16 , wherein the wherein the dielectric surrounds the plurality of fourth conductive pads and the top surface of the bridge, wherein the plurality of conductive layers includes a plurality of third vias that are coupled to the plurality of conductive pillars and fourth conductive pads, wherein the conductive ring layer includes one or more conductive materials, wherein the one or more conductive materials include copper, zinc oxide, ferric oxide, or copper oxide, wherein the bridge has a plurality of TSVs coupled to the plurality of third and fourth conductive pads of the bridge, wherein the bridge is coupled to a power source with the plurality of TSVs or a conductive layer of the FLIs when the conductive ring layer is a copper ring layer, and wherein the conductive layer of the FLIs is on and coupled to one or more of the plurality of first vias.