Method of forming a semiconductor device with memory cells, high voltage devices and logic devices on a substrate using a dummy area

Abstract

A method of forming a device on a semiconductor substrate having first, second, third and dummy areas, includes recessing the substrate upper surface in the first, second and dummy areas, forming a first conductive layer over the substrate, removing the first conductive layer from the third area and a second portion of the dummy area, forming a first insulation layer over the substrate, forming first trenches through the first insulation layer and into the substrate in the third area and the second portion of the dummy area, forming second trenches through the first insulation layer, the first conductive layer and into the substrate in the first and second areas and a first portion of the dummy area, and filling the first and second trenches with insulation material. Then, memory cells are formed in the first area, HV devices in the second area and logic devices in the third area.

What is claimed is: 
     
       1. A method of forming a semiconductor device, comprising:
 providing a substrate of semiconductor material that includes a first area, a second area, a third area and a dummy area, wherein the dummy area has first and second portions; 
 recessing an upper surface of the substrate in the first area, an upper surface of the substrate in the second area, and an upper surface of the substrate in the dummy area, the recessing relative to an upper surface of the substrate in the third area; 
 forming a first conductive layer disposed over and insulated from the upper surfaces in the first area, the second area, the third area and the dummy area; 
 removing the first conductive layer from the third area and from the second portion of the dummy area; 
 forming a first insulation layer in the first area, the second area, the third area and the dummy area; 
 forming first trenches through the first insulation layer and into the substrate in the third area and the second portion of the dummy area; 
 after the forming the first trenches, forming second trenches through the first insulation layer and the first conductive layer and into the substrate in the first area, the second area and the first portion of the dummy area; 
 filling the first and second trenches with insulation material; 
 after the filling of the first and second trenches, removing the first insulation layer from the first area, the second area, the third area and the dummy area; 
 forming a second insulation layer in the first area, the second area and the third area; 
 forming a second conductive layer on the second insulation layer in the first area, the second area and the third area; 
 performing one or more etches to selectively remove portions of the first and second conductive layers in the first area, to entirely remove the first and second conductive layers from the second area, and to entirely remove the second conductive layer from the third area, wherein the one or more etches result in pairs of stack structures in the first area with each of the stack structures including a control gate of the second conductive layer disposed over and insulated from a floating gate of the first conductive layer; 
 forming first source regions in the substrate of the first area each disposed between one of the pairs of stack structures; 
 forming a third conductive layer disposed over and insulated from the upper surfaces of the substrate in the first area, the second area and the third area; 
 forming a first protective insulation layer over the third conductive layer in the second area; 
 after the forming of the first protective insulation layer, forming a fourth conductive layer disposed over the first protective insulation layer in the second area, and over the third conductive layer in the first and third areas, wherein the third and fourth conductive layers form a composite conductive layer in the first area; 
 performing a chemical mechanical polish or etch-back to remove the third and fourth conductive layers from the third area, and to remove the fourth conductive layer from the second area; 
 performing an etch to recess an upper surface of the composite conductive layer below tops of the stack structures in the first area, leaving a plurality of erase gates of the composite conductive layer each respectively disposed over and insulated from one of the first source regions in the first area; 
 forming a second protective insulation layer over the composite conductive layer in the first area; 
 removing the second conductive layer and the second insulation layer from the third area; 
 after the removing of the second conductive layer and the second insulation layer from the third area, forming blocks of dummy conductive material disposed over and insulated from the upper surface of the substrate in the third area; 
 after the forming of the blocks of dummy conductive material in the third area, etching portions of the first and second protective insulation layers, portions of the composite conductive layer in the first area and portions of the third conductive layer in the second area to form a plurality of select gates of the composite conductive layer in the first area each disposed adjacent to one of the stack structures, and to form a plurality of HV gates of the third conductive layer in the second area each disposed over and insulated from the upper surface of the substrate; 
 forming first drain regions in the substrate of the first area each adjacent to one of the select gates; 
 forming second source regions in the substrate of the second area each adjacent one of the HV gates; 
 forming second drain regions in the substrate of the second area each adjacent one of the HV gates; 
 forming third source regions in the substrate of the third area each adjacent one of the blocks of dummy conductive material; 
 forming third drain regions in the substrate of the third area each adjacent one of the blocks of dummy conductive material; and 
 replacing each of the blocks of dummy conductive material of the third area with a block of metal material. 
 
     
     
       2. The method of  claim 1 , wherein each of the blocks of metal material is insulated from the upper surface of the substrate in the third area by a layer of high K insulation material. 
     
     
       3. The method of  claim 1 , wherein before the replacing, each of the blocks of dummy conductive material is insulated from the upper surface of the substrate in the third area by a layer of high K insulation material, and wherein the replacing further comprises forming each of the blocks of metal material on the layer of high K insulation material. 
     
     
       4. The method of  claim 1 , wherein each of the first, second, third and fourth conductive layers is formed of polysilicon or amorphous silicon. 
     
     
       5. The method of  claim 1 , further comprising:
 forming silicide on the first, second and third drain regions and on the second and third source regions. 
 
     
     
       6. The method of  claim 1 , further comprising:
 before the replacing, forming silicide on the select gates, the erase gates and the HV gates. 
 
     
     
       7. The method of  claim 1 , wherein the second insulation layer is an insulation layer having first oxide, nitride and second oxide sublayers. 
     
     
       8. The method of  claim 1 , wherein the forming of the blocks of dummy conductive material includes forming a logic insulation layer on the blocks of dummy conductive material and a hard mask layer on the logic insulation layer. 
     
     
       9. The method of  claim 8 , wherein before the replacing, further comprising:
 forming a layer of flowable material in the first, second and third areas; 
 removing a portion of the layer of flowable material to expose the hard mask layer; 
 removing the hard mask layer; and 
 removing the layer of flowable material. 
 
     
     
       10. The method of  claim 9 , further comprising:
 forming silicide on the select gates, the erase gates and the HV gates, wherein the logic insulation layer prevents the forming of silicide on the blocks of dummy conductive material.