System and method for aligned stitching

Abstract

A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor device comprising:
 forming a first active signal region over a semiconductor substrate; 
 forming a first conductive feature over the semiconductor substrate in the first active signal region; 
 forming a second active signal region over the semiconductor substrate; 
 forming a second conductive feature over the semiconductor substrate in the second active signal region; 
 forming a first alignment region between the first active signal region and the second active signal region, wherein the first conductive feature and the second conductive feature extend from a first side of the first alignment region to a second side of the first alignment region; 
 forming a plurality of first alignment features over the semiconductor substrate in the first alignment region; 
 forming a plurality of second alignment features adjacent the first active signal region opposite the first alignment region; and 
 singulating the semiconductor substrate, wherein the singulating the semiconductor substrate forms a singulated die comprising:
 the first active signal region, 
 the first conductive feature, 
 the second active signal region, 
 the second conductive feature, 
 the first alignment region, 
 the plurality of first alignment features, and 
 the plurality of second alignment features. 
 
 
     
     
       2. The method of  claim 1 , further comprising forming a third alignment feature in the first alignment region at a same level as one of the first alignment features in the first alignment region. 
     
     
       3. The method of  claim 2 , wherein the forming the third alignment feature in the first alignment region surrounds the one of the first alignment features in the first alignment region. 
     
     
       4. The method of  claim 2 , further comprising forming a first conductive line that electrically couples the first conductive feature to the second conductive feature, wherein a portion of the first conductive line is formed in the first alignment region between one of the first alignment features and the third alignment feature. 
     
     
       5. The method of  claim 4 , further comprising:
 forming a third active signal region over the semiconductor substrate different from the second active signal region; 
 forming a third conductive feature over the semiconductor substrate in the third active signal region; 
 forming a fourth conductive feature over the semiconductor substrate in the first active signal region, wherein the fourth conductive feature is different than the first conductive feature; 
 forming a second alignment region between the first active signal region and the third active signal region; and 
 forming a fourth alignment feature over the semiconductor substrate in the second alignment region. 
 
     
     
       6. The method of  claim 5 , further comprising forming a fifth alignment feature over the semiconductor substrate in the second alignment region. 
     
     
       7. The method of  claim 6 , further comprising forming a second conductive line that electrically couples the third conductive feature to the fourth conductive feature, wherein a portion of the second conductive line is formed in the second alignment region between the fourth alignment feature and the fifth alignment feature. 
     
     
       8. The method of  claim 7 , wherein after the forming the second conductive line the second conductive line is substantially orthogonal to the first conductive line. 
     
     
       9. A method of manufacturing a semiconductor device comprising:
 forming a first active signal region over a semiconductor substrate; 
 forming a second active signal region over the semiconductor substrate; 
 forming a transition region over the semiconductor substrate between the first active signal region and the second active signal region; 
 forming a first alignment mark within the transition region; 
 forming a second alignment mark within the transition region at a same level as the first alignment mark; 
 forming conductive routing extending over the semiconductor substrate through the transition region that electrically connects the first active signal region to the second active signal region, wherein after the forming the conductive routing the conductive routing has a first width across the transition region larger than a second width of the conductive routing within the first active signal region; and 
 performing a singulation process on the semiconductor substrate, wherein after the singulation process the first active signal region, the second active signal region, the transition region, the first alignment mark, the second alignment mark, and the conductive routing are all part of a singulated semiconductor die. 
 
     
     
       10. The method of  claim 9 , wherein the forming the first alignment mark comprises forming a first portion of the first alignment mark and forming a second portion of the first alignment mark surrounding the first portion. 
     
     
       11. The method of  claim 9 , further comprising forming a third alignment mark adjacent to the first active signal region and opposite the transition region. 
     
     
       12. The method of  claim 9 , wherein the forming the second alignment mark comprises aligning the second alignment mark with the first alignment mark. 
     
     
       13. The method of  claim 9 , wherein the forming the second alignment mark comprises misaligning the second alignment mark with the first alignment mark. 
     
     
       14. The method of  claim 9 , wherein the forming the first alignment mark comprises forming the first alignment mark as a square alignment mark. 
     
     
       15. A method of manufacturing a semiconductor device comprising:
 forming a first alignment mark over a semiconductor substrate to a first size; 
 forming a first active signal region over the semiconductor substrate; 
 forming a second active signal region over the semiconductor substrate on an opposite side of the first alignment mark from the first active signal region; 
 forming a conductive line adjacent to the first alignment mark connecting the first active signal region with the second active signal region, wherein the forming the conductive line comprises forming a first portion of the conductive line and forming a second portion of the conductive line that is shifted but parallel and continuous from the first portion of the conductive line; 
 forming a second alignment mark to the first size on an opposite side of the conductive line from the first alignment mark, wherein the forming the second alignment mark comprises misaligning the second alignment mark with the first alignment mark; and 
 singulating the semiconductor substrate, wherein after the singulating the semiconductor substrate the first alignment mark, the conductive line, and the second alignment mark are all part of a singulated die. 
 
     
     
       16. The method of  claim 15 , wherein the forming the first alignment mark further comprises:
 forming a first alignment feature; and 
 forming a second alignment feature surrounding the first alignment feature. 
 
     
     
       17. The method of  claim 16 , wherein after the forming the first alignment feature, the first alignment feature has a square shape. 
     
     
       18. The method of  claim 15 , further comprising forming a third alignment mark adjacent to the first active signal region and opposite to the second active signal region. 
     
     
       19. The method of  claim 18 , wherein after the forming the first alignment mark the first alignment mark has a first width and after the forming the third alignment mark the third alignment mark has a second width less than the first width. 
     
     
       20. The method of  claim 15 , wherein the forming the conductive line forms the first portion with a first width and forms the second portion with a second width different than the first width.