High voltage device with gate extensions

Abstract

The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate, and a drain region disposed within the substrate and separated from the source region. A plurality of separate isolation structures are disposed within the substrate. The plurality of separate isolation structures have outermost sidewalls that face one another and that are separated from one another. A gate electrode is disposed within the substrate. The gate electrode includes a base region disposed between the source region and the plurality of separate isolation structures and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of separate isolation structures.

What is claimed is: 
     
       1. An integrated chip, comprising:
 a source region disposed within a substrate; 
 a drain region disposed within the substrate and separated from the source region; 
 a plurality of separate isolation structures disposed within the substrate, wherein the plurality of separate isolation structures have outermost sidewalls that face one another and that are separated from one another; and 
 a gate electrode disposed within the substrate, wherein the gate electrode comprises a base region disposed between the source region and the plurality of separate isolation structures and a plurality of gate extensions extending outward from a side of the base region to directly over the plurality of separate isolation structures. 
 
     
     
       2. The integrated chip of  claim 1 , wherein the base region vertically extends from adjacent to respective ones of the plurality of gate extensions to below respective ones of the plurality of gate extensions. 
     
     
       3. The integrated chip of  claim 1 , wherein a sidewall of the base region extends between two neighboring ones of the plurality of gate extensions as viewed in a plan-view. 
     
     
       4. The integrated chip of  claim 1 , wherein the base region is arranged along a first end of the gate electrode and the plurality of gate extensions are arranged along an opposing second end of the gate electrode. 
     
     
       5. The integrated chip of  claim 1 ,
 wherein the source region is separated from the drain region along a first direction; and 
 wherein the base region has a width that is larger than widths of the plurality of gate extensions measured in a second direction that is perpendicular to the first direction. 
 
     
     
       6. The integrated chip of  claim 1 , wherein the plurality of gate extensions are directly between sidewalls of the plurality of separate isolation structures. 
     
     
       7. The integrated chip of  claim 1 , further comprising:
 a gate dielectric laterally and vertically separating the gate electrode from the substrate, wherein the gate electrode laterally and vertically contacts the plurality of separate isolation structures. 
 
     
     
       8. The integrated chip of  claim 1 , wherein the plurality of separate isolation structures cover a lower surface and an outermost sidewall of the plurality of gate extensions as viewed in a cross-sectional view. 
     
     
       9. The integrated chip of  claim 1 , wherein the substrate has a plurality of substrate fingers formed by sidewalls of the substrate that contact the plurality of separate isolation structures, the substrate fingers being interleaved with the plurality of gate extensions as viewed in a top-view. 
     
     
       10. An integrated chip, comprising:
 a source region disposed within a substrate; 
 a drain region disposed within the substrate and separated from the source region along a first direction; 
 one or more dielectric structures disposed within the substrate; 
 a gate electrode disposed within the substrate, wherein the gate electrode comprises a base region and one or more gate extensions extending outward from the base region in the first direction to over the one or more dielectric structures; and 
 a gate dielectric arranged along a sidewall and a lower surface of the gate electrode, wherein the gate electrode extends in the first direction past an outermost edge of the gate dielectric as viewed in a cross-sectional view. 
 
     
     
       11. The integrated chip of  claim 10 , wherein the gate dielectric has a first outermost sidewall that has a first length and an opposing second outermost sidewall that has a second length as viewed in the cross-sectional view, the second length being different than the first length. 
     
     
       12. The integrated chip of  claim 11 , wherein the second outermost sidewall is directly below the one or more gate extensions. 
     
     
       13. The integrated chip of  claim 10 , wherein the gate dielectric laterally straddles an interface between the one or more dielectric structures and the substrate. 
     
     
       14. The integrated chip of  claim 10 , wherein the base region, the one or more gate extensions, the gate dielectric, and the one or more dielectric structures have topmost surfaces that have been planarized to be substantially co-planar. 
     
     
       15. The integrated chip of  claim 10 , wherein the one or more gate extensions contact upper surfaces of the gate dielectric and the one or more dielectric structures. 
     
     
       16. An integrated chip, comprising:
 a source disposed within a substrate; 
 a drain disposed within the substrate and separated from the source; 
 one or more isolation structures disposed within the substrate; and 
 a gate disposed within the substrate between the source and the drain, wherein the gate comprises a base and one or more extensions extending outward from a sidewall of the base, the one or more extensions being embedded within the one or more isolation structures. 
 
     
     
       17. The integrated chip of  claim 16 , wherein the gate laterally extends from over the one or more isolation structures to past an outermost sidewall of the one or more isolation structures. 
     
     
       18. The integrated chip of  claim 16 , wherein the substrate has one or more substrate fingers that are interleaved with the one or more extensions as viewed in a top-view. 
     
     
       19. The integrated chip of  claim 16 ,
 wherein the one or more isolation structures separate the one or more extensions from the substrate along a first direction and along a second direction in a top-view, the first direction being perpendicular to the second direction; and 
 wherein the one or more isolation structures separate the one or more extensions from the substrate along a third direction in a cross-sectional view, the third direction being perpendicular to both the first direction and the second direction. 
 
     
     
       20. The integrated chip of  claim 16 , wherein both the base and the one or more extensions are arranged along a top-most surface of the gate.