Multi-bit structure

Abstract

An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

What is claimed is: 
     
       1. An integrated circuit, comprising:
 a multi-bit cell having a number M of a plurality of bit cells disposed in a plurality of cell rows having different cell height, M being a positive integer, 
 wherein a first bit cell and an (M/2)-th bit cell of the plurality of bit cells are arranged in a first column, and the (M/2)-th bit cell and an M-th bit cell of the plurality of bit cells are arranged in a last cell row of the plurality of cell rows. 
 
     
     
       2. The integrated circuit of  claim 1 , wherein the plurality of cell rows comprise a first plurality of cell rows with a first row height and a second plurality of cell rows with a second row height different from the first row height. 
     
     
       3. The integrated circuit of  claim 2 , wherein each of the plurality of bit cells includes one of the first plurality of cell rows and one of the second plurality of cell rows. 
     
     
       4. The integrated circuit of  claim 2 , wherein each of the plurality of bit cells includes an input stage cell and a data cell,
 wherein the input stage cell in each of the plurality of bit cells is included in one of the first plurality of cell rows, and the data cell in each of the plurality of bit cells is included in one of the second plurality of cell rows. 
 
     
     
       5. The integrated circuit of  claim 4 , wherein the first row height is greater than the second row height. 
     
     
       6. The integrated circuit of  claim 1 , wherein the first bit cell and an (M/2+1)-th bit cell of the plurality of bit cells abut each other along in a first direction. 
     
     
       7. The integrated circuit of  claim 1 , wherein an N-th bit cell and an (N+2)-th bit cell of the plurality of bit cells are included in the same cell row in the multi-bit cell, N being a positive integer and smaller than M. 
     
     
       8. The integrated circuit of  claim 7 , further comprising:
 a first interconnect crossing the first bit cell to the N-th bit cell; and 
 a second interconnect extending from the first bit cell to an (N+1)-th bit cell of the plurality of bit cells, 
 wherein the first to second interconnects are configured to transmit an output signal of the N-th bit cell as an input signal of the (N+1)-th bit cell. 
 
     
     
       9. The integrated circuit of  claim 1 , wherein the (M/2)-th bit cell and an (M/2+1)-th bit cell of the plurality of bit cells are arranged in different columns and different cell rows. 
     
     
       10. An integrated circuit, comprising:
 a first plurality of cell rows each having a first number of fin structures; 
 a second plurality of cell rows each having a second number, different from the first number, of fin structures; and 
 a plurality of bit cells in a multi-bit cell that have M bit cells each comprising an input stage cell in one of the first plurality of cell rows and a data cell in one of the second plurality of cell rows, 
 wherein the data cell of a first bit cell in the plurality of bit cells and the data cell of an (M/2+1)-th bit cell in the plurality of bit cells are in the same cell row in the first plurality of cell rows, wherein M is a positive integer. 
 
     
     
       11. The integrated circuit of  claim 10 , wherein the input stage cell of an (M/2)-th bit cell in the plurality of bit cells and the input stage cell of an M-th bit cell in the plurality of bit cells are arranged in the same cell row. 
     
     
       12. The integrated circuit of  claim 11 , wherein the data cell of the (M/2)-th bit cell and the data cell of the M-th bit cell are arranged in the same cell row. 
     
     
       13. The integrated circuit of  claim 10 , wherein a signal output by the data cell of the first bit cell and a signal output by the data cell of the (M/2+1)-th bit cell are transmitted in the same direction. 
     
     
       14. The integrated circuit of  claim 10 , wherein a row height of the first plurality of cell rows is greater than a row height of the second plurality of cell rows. 
     
     
       15. The integrated circuit of  claim 10 , further comprising:
 an interconnect extending in a column direction and shared by two bit cells, abutting each other along the column direction, of the plurality of bit cells. 
 
     
     
       16. The integrated circuit of  claim 10 , further comprising:
 an interconnect extending in a column direction to connect an (M/2)-th bit cell of the plurality of bit cells and the (M/2+1)-th bit cell, 
 wherein the first bit cell and the (M/2+1)-th bit cell are arranged at opposite sides of the interconnect. 
 
     
     
       17. A method, comprising:
 forming a plurality of input stage cells in a plurality of first rows each having a first number of fin structures and forming a plurality of data cells in a plurality of second rows each having a second number of fin structures, the first number being greater than the second number; 
 forming a first interconnect that extends in a first direction to couple a first data cell in the plurality of data cells to a first input stage cell in the plurality of input stage cells; and 
 forming a second interconnect extending through the plurality of first rows and the plurality of second rows to couple a second data cell, in a first column, in the plurality of data cells to a second input stage cell, in a second column adjacent to the first column, in the plurality of input stage cells. 
 
     
     
       18. The method of  claim 17 , wherein a third input stage cell arranged in a top row in the plurality of first rows and a third data cell arranged in a bottom row in the plurality of second rows are disposed diagonally. 
     
     
       19. The method of  claim 18 , further comprising:
 forming a metal segment extending in a row direction in the top row to couple the second interconnect to the second input stage cell, 
 wherein the metal segment and the second interconnect are in different layers. 
 
     
     
       20. The method of  claim 17 , wherein a row height of the plurality of first rows is different from a row height of the plurality of second rows.