Multiplexed thermal control wafer and coldplate

Abstract

Disclosed herein are systems and methods for controlling temperature(s) using a thermal control assembly (TCA) and a coldplate. The TCA comprises independently controllable thermal zones for controlling its top surface temperature. The thermal zones may be heater zones, cooling zones, or both. Energy input to the TCA may be selectively applied by, e.g., a thermal controller, such that different sets of thermal zones receive the energy at different times. In some embodiments, the energy input to the TCA may be selectively applied to two more independently controllable heater zones at the same time, the energy input to the TCA may be selectively applied to two or more independently controllable cooling zones at the same time, or both. In some aspects, less than all thermal zones may be activated at the same time, providing a higher power density for the thermal zones for a given energy input to the TCA.

The invention claimed is: 
     
       1. A method for controlling one or more temperatures of one or more devices under test (DUTs), the method comprising:
 receiving an energy input to a thermal control assembly (TCA); and 
 independently controlling a plurality of independently controllable thermal zones of the TCA, comprising:
 selectively controlling a plurality of independently controllable heater zones of the plurality of independently controllable thermal zones, comprising selectively applying the energy input to one or more of the plurality of independently controllable heater zones; and 
 selectively controlling a plurality of independently controllable cooling zones of the plurality of independent controllable thermal zones, 
 wherein the plurality of independently controllable heater zones and the plurality of independently controllable cooling zones are configured to maintain or change a temperature of a top surface of the TCA. 
 
 
     
     
       2. The method of  claim 1 , wherein selectively applying the energy input comprises selectively applying, by a demultiplexer, the energy input to two or more of the plurality of independently controllable heater zones. 
     
     
       3. The method of  claim 1 , wherein the receiving the energy input comprises receiving the input energy by a high-voltage electrical power source, wherein the high-voltage electrical power source provides a voltage of 200V or higher. 
     
     
       4. The method of  claim 1 , wherein the receiving the energy input comprises receiving the input energy by a high-voltage electrical power source, wherein the high-voltage electrical power source provides a voltage of 500V, 480V, 400V, 380V, 240V, 230V, or 220V. 
     
     
       5. The method of  claim 1 , wherein the plurality of independently controllable thermal zones maintaining or changing the temperature of the top surface of the TCA comprises maintaining or changing a temperature of a component placed on the top surface of the TCA. 
     
     
       6. The method of  claim 5 , wherein the component is a semiconductor wafer or panel. 
     
     
       7. The method of  claim 6 , wherein the semiconductor wafer or panel comprises singulated dies. 
     
     
       8. The method of  claim 1 , wherein the TCA is configured to receive a semiconductor wafer or panel on the top surface of the TCA, and a perimeter of the TCA is between 1-1.3 times greater than a perimeter of the semiconductor wafer or panel. 
     
     
       9. The method of  claim 1 , comprising:
 receiving a wafer under test (WUT) on the top surface of the TCA, the WUT comprising at least one chip, the at least one chip being a device under test (DUT). 
 
     
     
       10. The method of  claim 9 , wherein a size of at least one of the plurality of independently controllable thermal zones is substantially the same size as the at least one chip. 
     
     
       11. The method of  claim 9 , wherein an area of at least one of the plurality of independently controllable thermal zones is smaller than an area of the at least one chip. 
     
     
       12. The method of  claim 9 , wherein an area of two or more of the plurality of independently controllable thermal zones is equal to or greater than an area of the at least one chip. 
     
     
       13. The method of  claim 1 , comprising:
 electrically coupling the TCA to a wafer prober system, the wafer prober system comprising a probe card having probes that electrically couple to a device under test (DUT) during testing, wherein a size of at least one of the plurality of independently controllable thermal zones is substantially the same as a size of an area of the probe card. 
 
     
     
       14. The method of  claim 1 , comprising:
 electrically coupling the TCA to a wafer prober system, wherein the wafer prober system comprises a probe card having probes that electrically couple to a device under test (DUT) during testing, wherein a size of at least one of the plurality of independently controllable thermal zones is larger than a size of an area of the probe card. 
 
     
     
       15. The method of  claim 1 , comprising:
 electrically coupling the TCA to a wafer probe system, wherein the wafer probe system comprises a chuck base, and the TCA is configured to be located over the chuck base. 
 
     
     
       16. The method of  claim 1 , comprising:
 electrically coupling an electromagnetic interference (EMI) shield layer to an electrical ground, wherein the EMI shield layer is a conductive layer of a thermal control wafer (TCW). 
 
     
     
       17. The method of  claim 1 , comprising:
 configuring one or more resistive traces as heating-sensing elements, wherein the one or more resistive traces are included in a conductive layer of a thermal control wafer (TCW). 
 
     
     
       18. The method of  claim 1 , comprising:
 electrically coupling a two-wire connection to each of one or more resistive traces of a conductive layer of a thermal control wafer (TCW). 
 
     
     
       19. The method of  claim 18 , comprising:
 electrically coupling the two-wire connection to a pair of pins; 
 electrically coupling the pair of pins to a four-wire connection; and 
 electrically coupling the four-wire connection to circuitry outside of the TCW. 
 
     
     
       20. The method of  claim 1 , comprising:
 dissipating electrostatic charges using a thermal control wafer (TCW), wherein a top surface of the TCW is located adjacent to a semiconductor wafer or panel. 
 
     
     
       21. The method of  claim 1 , comprising:
 selectively electrically coupling the top surface of the TCW to ground or other electrical potential. 
 
     
     
       22. The method of  claim 1 , wherein at least one of the plurality of independently controllable heater zones has a power density of 0.05 W/mm 2  or higher. 
     
     
       23. The method of  claim 1 , wherein at least one of the plurality of independently controllable heater zones has a power density of 0.01 W/mm 2  or higher.