Method for forming a first and a second transistors array having plurality of first and semiconductor pillars

Abstract

Embodiments provide a semiconductor structure and a fabrication method. The method includes: providing a semiconductor substrate, the semiconductor substrate being provided with a plurality of first bit lines extending along a first direction; forming a first transistor array on the semiconductor substrate, the first transistor array including a plurality of first semiconductor pillars; forming first word lines, each of the plurality of first semiconductor pillars being connected to a corresponding one of the first word lines and a corresponding one of the plurality of first bit lines; forming a second transistor array on the first transistor array, the second transistor array including a plurality of second semiconductor pillars, and the plurality of first semiconductor pillars being corresponding to the plurality of second semiconductor pillars one to one; and forming second word lines and second bit lines to form a 2T0C semiconductor structure.

What is claimed is: 
     
       1. A method for fabricating a semiconductor structure, comprising:
 providing a semiconductor substrate, the semiconductor substrate being provided with a plurality of first bit lines extending along a first direction; 
 forming a first transistor array on the semiconductor substrate, the first transistor array comprising a plurality of first semiconductor pillars; 
 forming first word lines, each of the plurality of first semiconductor pillars being connected to a corresponding one of the first word lines and a corresponding one of the plurality of first bit lines; 
 forming a second transistor array on the first transistor array, the second transistor array comprising a plurality of second semiconductor pillars, and the plurality of first semiconductor pillars being corresponding to the plurality of second semiconductor pillars one to one; and 
 forming second word lines and second bit lines, each of the plurality of second semiconductor pillars being connected to a corresponding one of the second word lines and a corresponding one of the second bit lines. 
 
     
     
       2. The method for fabricating a semiconductor structure according to  claim 1 , wherein the plurality of first semiconductor pillars formed extend along a third direction and are arranged in an array in the first direction and a second direction; and the first word lines formed extend along the second direction and surround the plurality of first semiconductor pillars. 
     
     
       3. The method for fabricating a semiconductor structure according to  claim 2 , wherein the forming a first transistor array comprises:
 forming a first sacrificial layer, the first sacrificial layer covering a surface of the semiconductor substrate; 
 forming a plurality of first trenches extending along the first direction and a plurality of second trenches extending along the second direction, the plurality of first trenches and the plurality of second trenches being positioned in the first sacrificial layer, bottoms of the plurality of first trenches and bottoms of the plurality of the second trenches being flush with top surfaces of the plurality of first bit lines, and in the second direction, projections of the plurality of first trenches and projections of the plurality of first bit lines being parallel to each other and alternately arranged; 
 forming first isolation structures to fill the plurality of first trenches and the plurality of second trenches; and 
 removing the first sacrificial layer between adjacent two of the first isolation structures, and forming the plurality of first semiconductor pillars to fill a gap between adjacent two of the first isolation structures. 
 
     
     
       4. The method for fabricating a semiconductor structure according to  claim 3 , wherein the forming first word lines comprises:
 removing the first isolation structure by part of a height; 
 forming a first word line to cover a surface of the first isolation structure; 
 forming a second isolation structure to cover a surface of the first word line; and 
 forming a first spacer, the first spacer extending along the second direction and being positioned between adjacent two columns of the plurality of first semiconductor pillars, and in the first direction, the first spacer and each of the plurality of first semiconductor pillars being alternately arranged at intervals. 
 
     
     
       5. The method for fabricating a semiconductor structure according to  claim 2 , wherein the forming a first transistor array comprises:
 forming an initial first isolation structure, the initial first isolation structure covering a surface of the semiconductor substrate; 
 forming a plurality of first semiconductor holes extending along the third direction, the plurality of first semiconductor holes being positioned in the initial first isolation structure and arranged in an array in the first direction and the second direction, the plurality of first semiconductor holes exposing surfaces of the plurality of first bit lines, and a remaining part of the initial first isolation structure being used as a first isolation structure; and 
 forming the plurality of first semiconductor pillars to fill the plurality of first semiconductor holes. 
 
     
     
       6. The method for fabricating a semiconductor structure according to  claim 2 , wherein the forming a first transistor array and the forming first word lines comprise:
 forming an initial first isolation structure, the initial first isolation structure covering a surface of the semiconductor substrate; 
 forming a plurality of first isolation trenches extending along the second direction and a plurality of first semiconductor holes extending along the third direction, the plurality of first isolation trenches and the plurality of first semiconductor holes being positioned in the initial first isolation structure, the plurality of first semiconductor holes being arranged in an array in the first direction and the second direction and exposing surfaces of the plurality of first bit lines, and in the first direction, the plurality of first isolation trenches and the plurality of first semiconductor holes being alternately arranged at intervals; 
 forming a first spacer to fill the plurality of first isolation trenches, and forming the plurality of first semiconductor pillars to fill the plurality of first semiconductor holes; 
 removing the initial first isolation structure by part of a height, and a remaining part of the initial first isolation structure being used as the first isolation structure; 
 forming a first word line to cover a surface of the first isolation structure; and 
 forming a second isolation structure to cover the first word lines. 
 
     
     
       7. The method for fabricating a semiconductor structure according to  claim 1 , wherein after the first word lines are formed and before the second transistor layer is formed, the method further comprises:
 forming a contact structure, the contact structure being positioned on top surfaces of the plurality of first semiconductor pillars; and 
 forming a dielectric layer, the dielectric layer covering at least a surface of the contact structure. 
 
     
     
       8. The method for fabricating a semiconductor structure according to  claim 1 , wherein the plurality of second semiconductor pillars formed extend along the third direction and are arranged in an array in the first direction and the second direction; and the forming a second transistor array further comprises: forming a third isolation structure, the third isolation structure filling a gap between adjacent two of the plurality of second semiconductor pillars. 
     
     
       9. The method for fabricating a semiconductor structure according to  claim 8 , wherein the forming a second transistor array comprises:
 forming an initial third isolation structure, the initial third isolation structure being positioned above the first transistor array; 
 forming a plurality of second semiconductor holes extending along the third direction, the plurality of second semiconductor holes being positioned in the initial third isolation structure and corresponding to the plurality of first semiconductor pillars one to one, and a remaining part of the initial third isolation structure being used as the third isolation structure; and 
 forming the plurality of second semiconductor pillars to fill the plurality of second semiconductor holes. 
 
     
     
       10. The method for fabricating a semiconductor structure according to  claim 8 , wherein the forming a second transistor array comprises:
 forming a second semiconductor layer, the second semiconductor layer being positioned above the first transistor array; 
 forming a plurality of first grooves extending along the first direction and a plurality of second grooves extending along the second direction, the plurality of first grooves and the plurality of second grooves being positioned in the second semiconductor layer, and a remaining part of the second semiconductor layer being used as the plurality of second semiconductor pillars corresponding to the plurality of first semiconductor pillars one to one; and 
 forming a third isolation structure to fill the plurality of first grooves and the plurality of second grooves. 
 
     
     
       11. The method for fabricating a semiconductor structure according to  claim 8 , wherein the forming a second transistor array comprises:
 forming a second sacrificial layer, the second sacrificial layer being positioned above the first transistor array; 
 forming a plurality of third grooves extending along the first direction and a plurality of fourth grooves extending along the second direction, the plurality of third grooves and the plurality of fourth grooves being positioned in the second sacrificial layer, and a remaining part of the second sacrificial layer corresponding to the plurality of first semiconductor pillars one to one; 
 forming a third isolation structure to fill the plurality of third grooves and the plurality of fourth grooves; and 
 removing the second sacrificial layer in the third isolation structures, and forming the plurality of second semiconductor pillars to fill a gap between adjacent two of the third isolation structures. 
 
     
     
       12. The method for fabricating a semiconductor structure according to  claim 8 , wherein the forming second word lines and the forming second bit lines comprise:
 forming a first insulating layer, the first insulating layer covering a surface of the second transistor array; and 
 forming a plurality of second word lines and a plurality of second bit lines extending along the second direction, the plurality of second word lines and the plurality of second bit lines being positioned in the first insulating layer and being parallel to each other in the first direction and being alternately arranged at intervals, and in the second direction, a same one of the plurality of second word lines or a same one of the plurality of second bit lines being connected to a part of surfaces of adjacent two columns of the plurality of second semiconductor pillars. 
 
     
     
       13. The method for fabricating a semiconductor structure according to  claim 8 , wherein the forming second word lines and the forming second bit lines comprise:
 forming a second insulating layer, the second insulating layer covering a surface of the second transistor array; 
 forming a plurality of second word lines extending along the second direction, the plurality of second word lines being positioned in the second insulating layer, in the second direction, a same one of the plurality of second word lines being connected to a part of surfaces of adjacent two columns of the plurality of second semiconductor pillars, and in the first direction, surfaces of every two columns of the plurality of second semiconductor pillars being connected to a same one of the plurality of second word lines; 
 forming a third insulating layer, the third insulating layer covering surfaces of the plurality of second word lines and a surface of the second insulating layer; and 
 forming a plurality of second bit lines, the plurality of second bit lines comprising a plurality of second bit line contact lines extending along the third direction and a plurality of second bit line extension lines extending along the first direction, the plurality of second bit line contact lines being positioned in the second insulating layer and the third insulating layer, the plurality of second bit line extension lines being positioned in the third insulating layer, the plurality of second bit line contact lines being arranged in an array in the first direction and the second direction, the plurality of second bit line contact lines and the plurality of second word lines being alternately arranged at intervals in the first direction, each of the plurality of second bit line contact lines being connected to a part of surfaces of adjacent two of the plurality of second semiconductor pillars, and bottoms of the plurality of second bit line extension lines being connected to tops of the plurality of second bit line contact lines. 
 
     
     
       14. The method for fabricating a semiconductor structure according to  claim 1 , wherein a material for forming the plurality of first semiconductor pillars and the plurality of second semiconductor pillars comprises at least one or more of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), or Indium Tin Oxide (ITO).