IC structure with MFMIS memory cell and CMOS transistor

Abstract

An IC structure includes an MFMIS memory cell on a semiconductor substrate, and a CMOS transistor adjacent the MFMIS memory cell on the same semiconductor substrate. A method provides co-integration of the MFMIS memory cell with the CMOS transistor. The method may optionally co-integrate an MFIS memory cell. The IC structure and method provide a lower cost approach to forming MFMIS memory cells, which provide a number of advantages over MFIS memory cells.

What is claimed is: 
     
       1. An integrated circuit (IC) structure, comprising:
 a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory cell on a semiconductor substrate; and 
 a complementary metal-oxide semiconductor (CMOS) transistor adjacent the MFMIS memory cell on the semiconductor substrate 
 a metal-ferroelectric-insulator-semiconductor (MFIS) memory cell adjacent at least one of the MFMIS memory cell and the CMOS transistor, the MFIS memory cell sharing the semiconductor substrate with the MFMIS memory cell and the CMOS transistor. 
 
     
     
       2. The IC structure of  claim 1 , wherein the MFMIS memory cell includes an insulator layer and the CMOS transistor includes a gate insulator layer that are portions of a single insulator layer over the semiconductor substrate, and
 wherein the MFMIS memory cell includes a lower metal layer over the insulator layer of the MFMIS memory cell and the CMOS transistor includes a metal gate over the gate insulator layer of the CMOS transistor that are portions of a single metal layer. 
 
     
     
       3. The IC structure of  claim 2 , wherein the portions of the single insulator layer and the portions of the single metal layer are separated by an interlayer dielectric. 
     
     
       4. The IC structure of  claim 2 , wherein the MFMIS memory cell further includes a ferroelectric layer over the lower metal layer and an upper metal layer over the ferroelectric layer, and wherein the lower metal layer includes an electrode area extending laterally from under the upper metal layer and the ferroelectric layer. 
     
     
       5. The IC structure of  claim 4 , further comprising a first polysilicon electrode on the upper metal layer of the MFMIS memory cell, a second polysilicon electrode on the electrode area of the lower metal layer of the MFMIS memory cell, and a third polysilicon electrode on the metal gate of the CMOS transistor,
 wherein the first, second and third polysilicon electrodes are portions of a same polysilicon layer. 
 
     
     
       6. The IC structure of  claim 1 , further comprising a trench isolation separating the MFMIS memory cell and the CMOS transistor. 
     
     
       7. The IC structure of  claim 6 , wherein a portion of the semiconductor substrate extends through the trench isolation to contact an insulator layer of the MFMIS memory cell. 
     
     
       8. The IC structure of  claim 1 , wherein the MFMIS memory cell includes an upper metal layer over a ferroelectric layer over a lower metal layer over an insulator layer over the semiconductor substrate, and the MFIS memory cell includes an upper metal layer over a ferroelectric layer over an insulator layer over the semiconductor substrate, wherein the upper metal layers of the MFMIS memory cell and the MFIS memory are from a same metal layer and the insulator layers of the MFMIS memory cell and the MFIS memory are from a same insulator layer. 
     
     
       9. An integrated circuit (IC) structure, comprising:
 a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory cell, the MFMIS memory cell including an upper metal layer over a ferroelectric layer over a lower metal layer over an insulator layer over a semiconductor substrate, wherein the lower metal layer includes an electrode area extending laterally from under the upper metal layer and the ferroelectric layer; 
 a complementary metal-oxide semiconductor (CMOS) transistor adjacent the MFMIS memory cell and at least partially in the semiconductor substrate, the CMOS transistor including a metal gate over a gate insulator layer over the semiconductor substrate; 
 a trench isolation separating the MFMIS memory cell and the CMOS transistor; 
 a first polysilicon electrode on the upper metal layer of the MFMIS memory cell; 
 a second polysilicon electrode on the electrode area of the lower metal layer of the MFMIS memory cell; and 
 a third polysilicon electrode on the metal gate of the CMOS transistor. 
 
     
     
       10. The IC structure of  claim 9 , wherein the MFMIS memory cell and the CMOS transistor share the semiconductor substrate. 
     
     
       11. The IC structure of  claim 9 , further comprising an interlayer dielectric separating the MFMIS memory cell and the CMOS transistor. 
     
     
       12. The IC structure of  claim 9 , wherein the insulator layer of the MFMIS memory cell and the gate insulator layer of the CMOS transistor are portions of a same insulator layer over the semiconductor substrate, and the lower metal layer of the MFMIS memory cell and the metal gate of the CMOS transistor are portions of a same metal layer. 
     
     
       13. The IC structure of  claim 9 , wherein the first, second and third polysilicon electrodes are portions of a same polysilicon layer. 
     
     
       14. The IC structure of  claim 9 , further comprising a metal-ferroelectric-insulator-semiconductor (MFIS) memory cell adjacent at least one of the MFMIS memory cell and the CMOS transistor, the MFIS memory cell sharing the semiconductor substrate with the MFMIS memory cell and the CMOS transistor. 
     
     
       15. A method, comprising:
 forming a first trench isolation in a semiconductor substrate, the first trench isolation defining a first memory cell region and a transistor region; 
 forming a first metal layer over an insulator layer over the semiconductor substrate in the first memory cell region and the transistor region; 
 forming a ferroelectric layer over the insulator layer and a second metal layer over the ferroelectric layer in the first memory cell region, wherein an electrode area of the first metal layer extends laterally from under the second metal layer and the ferroelectric layer; 
 forming a polysilicon layer to form, in the first memory cell region, a first polysilicon electrode on the electrode area of the first metal layer and a second polysilicon electrode on the second metal layer and, in the transistor region, a third polysilicon electrode on the first metal layer; and 
 forming an interlayer dielectric between the first memory cell region and the transistor region. 
 
     
     
       16. The method of  claim 15 , wherein a portion of the semiconductor substrate extends through the first trench isolation to contact the insulator layer in the first memory cell region. 
     
     
       17. The method of  claim 15 , wherein the first metal layer and the insulator layer in the transistor region constitutes a metal gate of a complementary metal-oxide semiconductor (CMOS) transistor. 
     
     
       18. The method of  claim 15 , wherein forming the interlayer dielectric further includes forming the interlayer dielectric between the first polysilicon electrode on the electrode area of the first metal layer and the second polysilicon electrode on the second metal layer. 
     
     
       19. The method of  claim 15 , further comprising:
 forming a second trench isolation in the semiconductor substrate, the second trench isolation defining a second memory cell region adjacent at least one of the first memory cell region and the transistor region; 
 wherein forming the ferroelectric layer includes forming the ferroelectric layer over the semiconductor substrate in the second memory cell region and forming the second metal layer includes forming the second metal layer over the ferroelectric layer in the second memory cell region; and 
 wherein forming the interlayer dielectric includes forming the interlayer dielectric between the second memory cell region and the at least one of the first memory cell region and the transistor region. 
 
     
     
       20. The IC structure of  claim 12 , wherein the portions of the single insulator layer and the portions of the single metal layer are separated by an interlayer dielectric.