3D lateral patterning via selective deposition for ferroelectric devices

Abstract

In some embodiments, the present disclosure relates to a 3D memory device, including a plurality of gate lines interleaved between a plurality of dielectric layers in a vertical direction, the plurality of gate lines forming recesses between the plurality of dielectric layers; a source/drain line disposed next to the plurality of dielectric layers, spaced from the plurality of gate lines by the recesses in a lateral direction; a ferroelectric film arranged laterally between sidewalls of the plurality of gate lines and the source/drain line and confined within the recesses; and a semiconductor film disposed within the recesses and spacing the ferroelectric film from the source/drain line.

What is claimed is: 
     
       1. A method for forming a 3D memory device, the method comprising:
 forming a plurality of gate lines extending in a lateral direction, wherein the plurality of gate lines are vertically spaced apart from one another by a plurality of dielectric layers extending in the lateral direction; 
 forming a self-assembled monolayer (SAM) on outer surfaces of the plurality of dielectric layers; 
 forming a ferroelectric film on outer surfaces of the plurality of gate lines that are vertically separated from the SAM; 
 forming a semiconductor film on sidewalls of the ferroelectric film that are vertically separated from the SAM; and 
 forming source/drain lines along the plurality of gate lines extending in a vertical direction perpendicular to the lateral direction. 
 
     
     
       2. The method of  claim 1 , wherein the SAM is formed using alkyltrichlorosilane, and wherein the SAM is formed on outer surfaces of the plurality of dielectric layers in discrete segments that are separated by distances bridging the outer surfaces of the plurality of gate lines. 
     
     
       3. The method of  claim 1 , further comprising:
 forming the SAM using a plurality of chemical baths, wherein the plurality of chemical baths comprises an immersion into an alkyltrichlorosilane solution in toluene, sonication in toluene, an immersion in a first acetone chemical bath, an immersion in acetic acid, and an immersion in a second acetone chemical bath. 
 
     
     
       4. The method of  claim 1 , wherein the ferroelectric film and the semiconductor film are vertically spaced from the plurality of dielectric layers by the SAM due to bonding properties of a terminal functional group of the SAM. 
     
     
       5. The method of  claim 1 , wherein after the semiconductor film is deposited, the SAM is removed using an oxygen plasma treatment to ash the SAM. 
     
     
       6. The method of  claim 1 , further comprising:
 surrounding the semiconductor film with a conformal dielectric; 
 removing portions of the conformal dielectric to form source/drain holes separated by a second plurality of dielectric layers; and 
 filling the source/drain holes with a conductive material to form the source/drain lines. 
 
     
     
       7. The method of  claim 1 , wherein the SAM comprises:
 a head group that bonds to an oxide material in the plurality of dielectric layers, 
 a spacer with a thickness of approximately 1 to 3 nanometers, and 
 a terminal functional group that reacts with hydroxyl group (—OH) compounds. 
 
     
     
       8. A method for forming an integrated device, the method comprising: forming conductive layers and dielectric layers over a substrate,
 wherein the conductive layers are isolated from each other by the dielectric layers; 
 etching the conductive layers and the dielectric layers to form columns extending in a first lateral direction and spaced in a second lateral direction perpendicular to the first lateral direction; 
 etching the conductive layers to expose upper and lower surfaces of the dielectric layers; 
 forming a self-assembled monolayer (SAM) on outer sidewalls of the dielectric layers; 
 forming a ferroelectric film on exposed surfaces of the conductive layers; 
 forming a semiconductor film on exposed surfaces of the ferroelectric film; 
 forming a conformal dielectric covering the semiconductor film; 
 etching the conformal dielectric to form openings extending in a vertical direction and exposing portions of the semiconductor film; and 
 forming source/drain lines within the openings. 
 
     
     
       9. The method of  claim 8 , wherein the conductive layers have outer sidewalls facing the second lateral direction;
 wherein after forming the SAM, the SAM covers the exposed upper and lower surfaces of the dielectric layers and a first portion of the outer sidewalls of the conductive layers; and 
 wherein after forming the ferroelectric film, the ferroelectric film is spaced from the dielectric layers by the SAM. 
 
     
     
       10. The method of  claim 8 , wherein the SAM is further formed on the upper and lower surfaces of the dielectric layers. 
     
     
       11. The method of  claim 8 , wherein the exposed surfaces of the ferroelectric film extend from a lower dielectric layer to an upper dielectric layer of the dielectric layers. 
     
     
       12. The method of  claim 8 , further comprising removing the SAM before forming the conformal dielectric, wherein the conformal dielectric contacts the outer sidewalls of the dielectric layers after being formed. 
     
     
       13. The method of  claim 12 , wherein forming the conformal dielectric results in the conformal dielectric contacting outer sidewalls of the conductive layers. 
     
     
       14. The method of  claim 8 , wherein after the conformal dielectric is etched, the openings are spaced in the first lateral direction by remaining portions of the conformal dielectric. 
     
     
       15. A method for forming an integrated device, the method comprising:
 forming a plurality of gate lines extending in a first lateral direction and spaced from each other by a plurality of dielectric layers in a vertical direction, wherein the plurality of gate lines have first outer sidewalls facing a second lateral direction perpendicular to the first lateral direction, and the plurality of dielectric layers have second outer sidewalls facing the second lateral direction; 
 forming a ferroelectric film on the first outer sidewalls and between the second outer sidewalls, the ferroelectric film having third outer sidewalls facing the second lateral direction; 
 forming a semiconductor film on the third outer sidewalls and between the second outer sidewalls, the semiconductor film having fourth outer sidewalls facing the second lateral direction; 
 forming a conformal dielectric covering the fourth outer sidewalls and the second outer sidewalls; 
 etching the conformal dielectric to form openings extending in the vertical direction and exposing portions of the fourth outer sidewalls; and 
 forming source/drain lines within the openings. 
 
     
     
       16. The method of  claim 15 , further comprising:
 forming a self-assembled monolayer (SAM) on the second outer sidewalls after forming the plurality of gate lines, the SAM having fifth outer sidewalls facing the second lateral direction, wherein the fifth outer sidewalls remain exposed after forming the ferroelectric film and the semiconductor film; and 
 removing the SAM before forming the conformal dielectric. 
 
     
     
       17. The method of  claim 16 , further comprising etching the plurality of gate lines, resulting in the first outer sidewalls being separated from the second outer sidewalls in the second lateral direction,
 wherein the SAM is also formed on upper and lower surfaces of the plurality of dielectric layers that are exposed in the etching of the plurality of gate lines, and 
 wherein the SAM covers a portion of the first outer sidewalls, resulting in the ferroelectric film being spaced from the plurality of dielectric layers by the SAM after the ferroelectric film is formed. 
 
     
     
       18. The method of  claim 15 , wherein the ferroelectric film comprises a plurality of strips of ferroelectric material on the first outer sidewalls and separated by the second outer sidewalls in the vertical direction. 
     
     
       19. The method of  claim 18 , wherein after the source/drain lines are formed, a first source/drain line and a second source/drain line of the source/drain lines contact a first strip and a second strip of the plurality of strips. 
     
     
       20. The method of  claim 15 , wherein the conformal dielectric extends between the ferroelectric film and the plurality of dielectric layers.