Semiconductor structures and methods of forming the same

Abstract

Passive devices are provided. In an embodiment, a passive device includes a substrate comprising a first region and a second region, a first lower contact feature and a second lower contact feature in a dielectric layer and directly over the first region and the second region, respectively, a first vertical stack of conductive features disposed over the first region, a metal-insulator-metal (MIM) capacitor disposed over the second region and comprising a vertical stack of conductor plates, a first contact via extending through the first vertical stack of conductive features and electrically coupled to the first lower contact feature, and a second contact via extending through a portion of the vertical stack of conductor plates and electrically coupled to the second lower contact feature. A number of conductive features penetrated by the first contact via is different than a number of conductor plates penetrated by the second contact via.

What is claimed is: 
     
       1. A semiconductor structure, comprising:
 a substrate comprising a first region and a second region; 
 a first lower contact feature and a second lower contact feature in a dielectric layer and directly over the first region and the second region, respectively; 
 first conductive features disposed over the first region; 
 second conductive features disposed over the second region, physically separated from the first conductive features, and comprising conductor plates of a metal-insulator-metal (MIM) capacitor and dummy plates physically separated from the conductor plates; 
 a first contact via extending through the first conductive features and electrically coupled to the first lower contact feature; and 
 a second contact via extending through a part of the conductor plates and at least one of the dummy plates and electrically coupled to the second lower contact feature, 
 wherein a number of the first conductive features penetrated by the first contact via is greater than a number of the second conductive features penetrated by the second contact via. 
 
     
     
       2. The semiconductor structure of  claim 1 , wherein the MIM capacitor comprises a number of M conductor plates, the first conductive features comprise a number of N conductive features, wherein M≥N>1. 
     
     
       3. The semiconductor structure of  claim 2 , wherein the conductor plates of the MIM capacitor comprises a first conductor plate, a second conductor plate, a third conductor plate, a fourth conductor plate, and a fifth conductor plate stacked bottom to up, and the second contact via extends through the fifth conductor plate, the third conductor plate, and the first conductor plate. 
     
     
       4. The semiconductor structure of  claim 2 , further comprising:
 a third lower contact feature in the dielectric layer and directly over the second region; and 
 a third contact via extending through a remaining part of the conductor plates, 
 wherein the second contact via and the third contact via penetrate a same number of conductive features of the second conductive features. 
 
     
     
       5. The semiconductor structure of  claim 1 , a width of the first contact via is greater than a width of the second contact via. 
     
     
       6. A semiconductor structure, comprising:
 a substrate comprising a first region and a second region; 
 a first lower contact feature in a dielectric layer and disposed directly over the first region; 
 a second lower contact feature in the dielectric layer and directly over the second region; 
 an integrated structure over the dielectric layer and comprising N first dummy conductive features over the first region and a metal-insulator-metal (MIM) capacitor and D second dummy conductive features over the second region, the MIM capacitor having M conductor plates, wherein D >0; 
 a first contact via penetrating the integrated structure and in direct contact with the first lower contact feature and each of the N first dummy conductive features, M≥N>1; 
 a second contact via penetrating the integrated structure and in direct contact with the second lower contact feature and M′ conductor plates of the M conductor plates, wherein N>M′>0, 
 wherein N is greater than a sum of M′ and a number of the D second dummy conductive features penetrated by the second contact via. 
 
     
     
       7. The semiconductor structure of  claim 6 , wherein M=5, M′=2. 
     
     
       8. The semiconductor structure of  claim 6 , wherein a top surface of the first contact via is coplanar with a top surface of the second contact via, and a depth of the first contact via is different than a depth of the second contact via. 
     
     
       9. The semiconductor structure of  claim 6 , wherein the first lower contact feature and the second lower contact feature each comprises a concave top surface. 
     
     
       10. The semiconductor structure of  claim 6 , wherein the first contact via spans a width greater than a width of the second contact via. 
     
     
       11. The semiconductor structure of  claim 6 , wherein the MIM capacitor comprises:
 a bottom plate on the dielectric layer and directly over the second lower contact feature, 
 a first insulator layer over the bottom plate, 
 a middle plate over the first insulator layer, 
 a second insulator layer over the middle plate, and 
 a top plate over the second insulator layer and directly over the second lower contact feature, and 
 wherein the second contact via extends through the top plate and the bottom plate. 
 
     
     
       12. The semiconductor structure of  claim 11 , wherein the N first dummy conductive features comprise:
 a first dummy conductive feature directly over the first lower contact feature; 
 a second dummy conductive feature directly over both the first dummy conductive feature and the first lower contact feature; and 
 a third dummy conductive feature directly over both the second dummy conductive feature and the first lower contact feature, 
 wherein the first dummy conductive feature and the bottom plate have the same composition and thickness, 
 wherein the second dummy conductive feature and the middle plate have the same composition and thickness, and 
 wherein the third dummy conductive feature and the top plate have the same composition and thickness. 
 
     
     
       13. A semiconductor structure, comprising:
 a metal-insulator-metal (MIM) capacitor having M conductor plates; 
 a first conductive feature disposed under the MIM capacitor; 
 a dummy conductive feature physically isolated from conductor plates of the MIM capacitor, 
 a first via disposed over the first conductive feature and electrically coupling the MIM capacitor to the first conductive feature, a top surface of the first via having a first width, wherein a portion of the first via extends into the first conductive feature and has a first depth, wherein the first via extends through the dummy conductive feature and M′ conductor plates of the M conductor plates, M′ is a positive integer and is less than M; 
 a plurality of vertically stacked conductive layers adjacent to the MIM capacitor, wherein a number of the plurality of vertically stacked conductive layers is greater than M′, and a difference between the number of the plurality of vertically stacked conductive layers and M′ is greater than 1; 
 a second conductive feature disposed under the plurality of vertically stacked conductive layers, wherein a top surface of the first conductive feature is substantially coplanar with a top surface of the second conductive feature; and 
 a second via extending through the plurality of vertically stacked conductive layers to contact the second conductive feature, a top surface of the second via having a second width, wherein a portion of the second via extends into the second conductive feature and has a second depth; 
 wherein the second depth is greater than the first depth, and the second width is greater than the first width. 
 
     
     
       14. The semiconductor structure of  claim 13 ,
 wherein the number of the plurality of vertically stacked conductive layers is less than M. 
 
     
     
       15. The semiconductor structure of  claim 13 ,
 wherein each of the first via and the second via has a curved bottom surface. 
 
     
     
       16. The semiconductor structure of  claim 13 , wherein a composition and a thickness of one of the plurality of vertically stacked conductive layers are the same as a composition and a thickness of a conductor plate of the MIM capacitor. 
     
     
       17. The semiconductor structure of  claim 13 ,
 wherein the MIM capacitor further comprises a plurality of dielectric layers interleaving the M conductor plates, and 
 wherein two adjacent conductive layers of the plurality of vertically stacked conductive layers are separated by one or more dielectric layers of the plurality of dielectric layers. 
 
     
     
       18. The semiconductor structure of  claim 13 , further comprising:
 a third conductive feature disposed under the MIM capacitor and adjacent to the first conductive feature; 
 and 
 a third via extending through M″ conductor plates of the M conductor plates electrically coupling the MIM capacitor to the third conductive feature, wherein M″ is different from M′. 
 
     
     
       19. The semiconductor structure of  claim 13 , wherein M=5. 
     
     
       20. The semiconductor structure of  claim 13 , wherein the number of the plurality of vertically stacked conductive layers is less than or equal to M.