Embedded package with shielding pad

Abstract

A semiconductor package includes a laminate package substrate, first and second power transistor dies embedded within the laminate package substrate, a driver die embedded within the laminate package substrate, a plurality of I/O routings electrically connected with I/O terminals of the driver die, a switching signal pad electrically connected with a second load terminal of the first power transistor die and a first load terminal of the second power transistor die, and a shielding pad that is configured to electrically shield at least one of the I/O routings from the switching signal pad during operation of the first and second power transistor dies.

The invention claimed is: 
     
       1. A semiconductor package, comprising:
 a laminate package substrate comprising a first outer metallization layer at least partially at a first outer side of the laminate package substrate, and a first interior metallization layer that is below the first outer metallization layer; 
 first and second power transistor dies embedded within the laminate package substrate, the first and second power transistor dies each comprising a first load terminal and a second load terminal; 
 a driver die embedded within the laminate package substrate and comprising a plurality of I/O terminals facing the first outer side of the semiconductor package; 
 a plurality of I/O routings formed in the first interior metallization layer and electrically connected with the I/O terminals of the driver die; 
 a switching signal pad formed in the first outer metallization layer and electrically connected with the second load terminal of the first power transistor die and the first load terminal of the second power transistor die; and 
 a shielding pad formed in the first outer metallization layer that is configured to electrically shield at least one of the I/O routings from the switching signal pad during operation of the first and second power transistor dies. 
 
     
     
       2. The semiconductor package of  claim 1 , wherein the I/O routings comprise a first I/O routing that conveys a current magnitude signal, and wherein the shielding pad overlaps with the first I/O routing. 
     
     
       3. The semiconductor package of  claim 2 , wherein the driver die is configured to adjust a gate signal that switches one of the first and second power transistor dies based upon the current magnitude signal from the first I/O routing. 
     
     
       4. The semiconductor package of  claim 2 , wherein the shielding pad completely overlaps with the first I/O routing. 
     
     
       5. The semiconductor package of  claim 1 , wherein the laminate package substrate further comprises an electrically insulating layer disposed at the first outer side, and wherein the shielding pad is completely covered by the electrically insulating layer. 
     
     
       6. The semiconductor package of  claim 1 , wherein the shielding pad is externally accessible at the first outer side. 
     
     
       7. The semiconductor package of  claim 1 , wherein the second load terminal of the first power transistor die and the first load terminal of the second power transistor die each face the first outer side of the semiconductor package, and wherein the switching signal pad overlaps with the second load terminal of the first transistor die and the first load terminal of the second transistor die. 
     
     
       8. The semiconductor package of  claim 1 , wherein the shielding pad is an electrically floating node of the semiconductor package. 
     
     
       9. The semiconductor package of  claim 1 , wherein the shielding pad is connected to an AGND node of the semiconductor package. 
     
     
       10. The semiconductor package of  claim 1 , wherein the switching signal pad and the shielding pad are from the only two nodes of the of the semiconductor package that are formed in the first outer metallization layer. 
     
     
       11. The semiconductor package of  claim 1 , wherein the first and second power transistor dies each comprise a gate terminal, wherein the gate terminal of the first power transistor die faces the first outer side of the semiconductor package, and wherein the gate terminal of the second power transistor die faces away from the first outer side of the semiconductor package. 
     
     
       12. The semiconductor package of  claim 1 , wherein the first outer metallization layer is a closest metallization layer of the laminate package substrate to the first interior metallization layer. 
     
     
       13. The semiconductor package of  claim 1 , wherein the first and second power transistor dies form a high-side switch and a low-side switch, respectively, of a half bridge circuit, and wherein the driver die is configured to control the half bridge circuit using the I/O routings. 
     
     
       14. A method of forming a semiconductor package, the method comprising:
 forming a laminate package substrate comprising a first outer metallization layer and a first interior metallization layer that is below the first outer metallization layer, the first outer metallization layer being disposed at least partially at a first outer side of the laminate package substrate; 
 embedding first and second power transistor dies within the laminate package substrate, the first and second power transistor dies each comprising a first load terminal and a second load terminal; 
 embedding a driver die within the laminate package substrate, the driver die comprising a plurality of I/O terminals facing the first outer side of the semiconductor package; 
 forming a plurality of I/O routings in the first interior metallization layer that are electrically connected with the I/O terminals of the driver die; 
 forming a switching signal pad in the first outer metallization layer that is electrically connected with the second load terminal of the first power transistor die and the first load terminal of the second power transistor die; and 
 forming a shielding pad in the first outer metallization layer that is configured to electrically shield at least one of the I/O routings from the switching signal pad during operation of the first and second power transistor dies. 
 
     
     
       15. The method of  claim 14 , wherein forming the laminate package substrate comprises forming a core dielectric region, a first laminate layer over the core dielectric region, and a second laminate layer over the first laminate layer, wherein the first and second power transistor dies and the driver die are embedded within openings in the core dielectric region, wherein the first interior metallization layer is formed on an upper surface of the first laminate layer, and wherein the first outer metallization layer is formed on an upper surface of the second laminate layer. 
     
     
       16. The method of  claim 15 , wherein each of the first and second laminate layers comprise pre-preg material and/or resin material. 
     
     
       17. The method of  claim 14 , wherein the I/O routings comprise a first I/O routing that conveys a current magnitude signal, and wherein the shielding pad overlaps with the first I/O routing. 
     
     
       18. The method of  claim 17 , wherein the driver die is configured to adjust a gate signal that switches one of the first and second power transistor dies based upon the current magnitude signal from the first I/O routing. 
     
     
       19. The method of  claim 14 , wherein the shielding pad is formed to be an electrically floating node of the semiconductor package. 
     
     
       20. The method of  claim 14 , wherein the shielding pad is formed to be an AGND node of the semiconductor package.