HV device and method for manufacturing same

Abstract

The present application discloses an HV device, comprising: a gate dielectric layer formed in a first trench, a gate conductive material layer formed on the surface of the gate dielectric layer, and a second dielectric layer filling a second trench formed between a second side face of a drain shallow trench isolation and a first side face of the first trench. The depths of the first trench and the second trench are equal. The first trench and the second trench connect with each other to form an overall trench. Bottom surfaces of the second dielectric layer and the gate dielectric layer are flush with each other. A first side face of the gate conductive material layer extends to the surface of the second dielectric layer. The present application also discloses a method for manufacturing the HV device.

What is claimed is: 
     
       1. An HV device, comprising:
 a gate dielectric layer, wherein the gate dielectric layer is formed in a first trench, wherein the first trench is formed by etching a semiconductor substrate, and wherein a top surface of the gate dielectric layer is configured to be flush with a top surface of the semiconductor substrate; 
 a gate conductive material layer, formed on the top surface of the gate dielectric layer; 
 a first high voltage well region, wherein the first high voltage well region is formed on the semiconductor substrate and is doped with a second conductivity type of impurity; 
 a drain structure, wherein the drain structure is formed in the first high voltage well region outside a first side face of the gate dielectric layer; 
 a source structure, wherein the source structure is formed in the first high voltage well region outside a second side face of the gate dielectric layer;
 wherein the drain structure comprises a drain high voltage diffusion region doped with a first conductivity type of impurity, a drain shallow trench isolation, a second dielectric layer, and a drain region heavily doped with the first conductivity type of impurity; 
 wherein the drain high voltage diffusion region is formed in the first high voltage well region, and wherein the drain shallow trench isolation is formed in a selected region of the drain high voltage diffusion region; 
 
 a second trench, wherein the second trench is formed in the drain high voltage diffusion region between a second side face of the drain shallow trench isolation and a first side face of the first trench, and wherein the second dielectric layer is formed in the second trench;
 wherein the second side face of the drain shallow trench isolation is aligned with a first side face of the second trench; wherein a second side face of the second trench is aligned with the first side face of the first trench; wherein a depth of the drain shallow trench isolation is greater than a depth of the first trench; 
 wherein the depth of the first trench is equal to a depth of the second trench, and wherein the first trench and the second trench connect with each other to form an overall trench; wherein a bottom surface of the second dielectric layer and a bottom surface of the gate dielectric layer are flush with each other; wherein a first side face of the gate conductive material layer extends to a surface of the second dielectric layer, such that a region covered by the gate conductive material layer has no sharp corner and is away from a bottom sharp corner of the drain shallow trench isolation; 
 
 wherein the drain region is formed in a surface region of the drain high voltage diffusion region outside a first side face of the drain shallow trench isolation, and wherein a junction depth of the drain region is less than a thickness of the second dielectric layer;
 wherein the source structure comprises a source high voltage diffusion region and a source region heavily doped with the first conductivity type of impurity, wherein the source high voltage diffusion region is formed in the first high voltage well region, and wherein the source region is formed in a surface region of the source high voltage diffusion region; and wherein the first side face of the gate dielectric layer extends into the drain high voltage diffusion region, and wherein the second side face of the gate dielectric layer extends into the source high voltage diffusion region; and wherein a channel region includes the first high voltage well region at a bottom of the gate dielectric layer. 
 
 
     
     
       2. The HV device according to  claim 1 , wherein the first trench and the second trench are formed simultaneously by means of a same etching process. 
     
     
       3. The HV device according to  claim 2 , wherein an active region is defined in the semiconductor substrate by a shallow trench isolation, wherein the active region includes a portion of the semiconductor substrate enclosed by the shallow trench isolation;
 wherein the shallow trench isolation includes the drain shallow trench isolation in a formation region of the drain structure; wherein the active region comprises a first active region located in the channel region, and wherein a first side face of the first active region is defined by the second side face of the drain shallow trench isolation; 
 wherein an etching region of the first trench is defined by using a mask of the gate conductive material layer; and 
 wherein the first side face of the first active region extends towards one side of the drain region to the outside of the first side face of the gate conductive material layer, and wherein an etching region of the second trench is formed by extending the etching region of the first trench to a surface of the drain shallow trench isolation. 
 
     
     
       4. The HV device according to  claim 3 , wherein the second dielectric layer and the gate dielectric layer are formed simultaneously by a same process. 
     
     
       5. The HV device according to  claim 4 , wherein a material of the gate dielectric layer comprises silicon oxide or a high dielectric constant material. 
     
     
       6. The HV device according to  claim 5 , wherein the gate conductive material layer comprises a metal gate. 
     
     
       7. The HV device according to  claim 1 , wherein the HV device is of an asymmetrical structure, and wherein the source region is self-aligned with the second side face of the gate dielectric layer;
 alternatively, the HV device is of a symmetrical structure, wherein a source shallow trench isolation is formed in the source high voltage diffusion region, wherein a first side face of the source shallow trench isolation is aligned with the second side face of the gate dielectric layer, wherein the source region is self-aligned with a second side face of the source shallow trench isolation; and wherein the source shallow trench isolation and the drain shallow trench isolation present a symmetrical structure. 
 
     
     
       8. The HV device according to  claim 1 , wherein a peripheral high voltage diffusion region doped with the second conductivity type of impurity is also formed in the first high voltage well region in the periphery of the HV device, wherein a substrate pickup region heavily doped with the second conductivity type of impurity is formed on a surface of the peripheral high voltage diffusion region, and wherein the substrate pickup region is electrically connected to the source region. 
     
     
       9. A method for manufacturing an HV device, comprising following steps:
 step  1 , providing a semiconductor substrate, wherein a first high voltage well region doped with a second conductivity type of impurity is formed on the semiconductor substrate, a drain high voltage diffusion region doped with a first conductivity type of impurity and a source high voltage diffusion region are formed in selected regions of the first high voltage well region, and wherein a drain shallow trench isolation is formed in a selected region of the drain high voltage diffusion region; 
 step  2 , defining an etching region of a first trench, and etching the semiconductor substrate in the etching region of the first trench to form the first trench; and 
 defining an etching region of a second trench, and etching the semiconductor substrate in the etching region of the second trench to form the second trench,
 wherein the second trench is formed in the drain high voltage diffusion region between a second side face of the drain shallow trench isolation and a first side face of the first trench; 
 wherein the second side face of the drain shallow trench isolation is aligned with a first side face of the second trench; wherein a second side face of the second trench is aligned with the first side face of the first trench; wherein a depth of the drain shallow trench isolation is greater than a depth of the first trench; and 
 wherein the depth of the first trench is equal to a depth of the second trench, and the first trench and the second trench connect with each other to form an overall trench; 
 
 step  3 , filling the first trench with a gate dielectric layer, and filling the second trench with a second dielectric layer,
 wherein a top surface of the gate dielectric layer and a top surface of the second dielectric layer are both flush with a top surface of the semiconductor substrate; 
 wherein a bottom surface of the second dielectric layer and a bottom surface of the gate dielectric layer are flush with each other; 
 wherein a first side face of the gate dielectric layer extends into the drain high voltage diffusion region, and wherein a second side face of the gate dielectric layer extends into the source high voltage diffusion region; and 
 wherein a channel region includes the first high voltage well region at a bottom of the gate dielectric layer; 
 
 step  4 , forming a gate conductive material layer, wherein the gate conductive material layer is located on the top surface of the gate dielectric layer and extends to a surface of the second dielectric layer, and wherein a region covered by the gate conductive material layer has no sharp corner and is away from a bottom sharp corner of the drain shallow trench isolation; and 
 step  5 , performing source and drain injection to form a source region and a drain region both heavily doped with the first conductivity type of impurity,
 wherein the drain region is formed in a surface region of the drain high voltage diffusion region outside a first side face of the drain shallow trench isolation in a self-aligned manner, and wherein a junction depth of the drain region is less than a thickness of the second dielectric layer; 
 wherein the source region is formed in a surface region of the source high voltage diffusion region; 
 wherein a drain structure is located in the first high voltage well region outside the first side face of the gate dielectric layer, and a source structure is located in the first high voltage well region outside the second side face of the gate dielectric layer; 
 wherein the drain structure comprises the drain high voltage diffusion region, the drain shallow trench isolation, the second dielectric layer, and the drain region; and 
 wherein the source structure comprises the source high voltage diffusion region and the source region. 
 
 
     
     
       10. The method for manufacturing the HV device according to  claim 9 , wherein the first trench and the second trench are formed simultaneously by a same etching process in step  2 . 
     
     
       11. The method for manufacturing the HV device according to  claim 10 , wherein an active region is defined by a shallow trench isolation in step  1  in the semiconductor substrate, and wherein the active region comprises a region enclosed by the shallow trench isolation in the semiconductor substrate; wherein the drain shallow trench isolation is located in a formation region of the drain structure, wherein the active region where the channel region is located is a first active region, and a first side face of the first active region is aligned with the second side face of the drain shallow trench isolation;
 wherein the first side face of the first active region extends towards one side of the drain region to an outside of a first side face of the gate conductive material layer; 
 wherein the etching region of the first trench is defined by using a mask of the gate conductive material layer in step  2 ; and 
 wherein the etching region of the second trench is formed by extending the etching region of the first trench to a surface of the drain shallow trench isolation. 
 
     
     
       12. The method for manufacturing the HV device according to  claim 10 , wherein the second dielectric layer and the gate dielectric layer are formed simultaneously by a same process in step  3 . 
     
     
       13. The method for manufacturing the HV device according to  claim 10 , wherein a material of the gate dielectric layer in step  3  comprises silicon oxide or a high dielectric constant material. 
     
     
       14. The method for manufacturing the HV device according to  claim 13 , wherein the gate conductive material layer in step  4  comprises a metal gate. 
     
     
       15. The method for manufacturing the HV device according to  claim 9 , wherein the HV device is of an asymmetrical structure, and the source region is self-aligned with the second side face of the gate dielectric layer in step  5 ;
 alternatively, the HV device is of a symmetrical structure, wherein a source shallow trench isolation is formed in the source high voltage diffusion region in step  1 , a first side face of the source shallow trench isolation is aligned with the second side face of the gate dielectric layer in step  3 , and wherein the source region is self-aligned with a second side face of the source shallow trench isolation in step  5 ; and the source shallow trench isolation and the drain shallow trench isolation present a symmetrical structure. 
 
     
     
       16. The method for manufacturing the HV device according to  claim 9 , wherein a peripheral high voltage diffusion region doped with the second conductivity type of impurity is formed in the first high voltage well region on a periphery of the HV device in step  1 ;
 after step  5 , the method further comprises performing source and drain injection to form a substrate pickup region which is heavily doped with the second conductivity type of impurity, on a surface of the peripheral high voltage diffusion region, and wherein the substrate pickup region is electrically connected to the source region.