Semiconductor package

Abstract

A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region. Each of the connection terminals may include a convex portion at a lateral surface thereof, which protrudes beyond a lateral surface of a respective first pad and a lateral surface of a respective second pad. The convex portion may protrude in a direction away from a center of the first die. Protruding distances of the convex portions may increase in a direction from the center of the first die toward an outside of the first die.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a first die having a central region and a peripheral region that surrounds the central region;   through electrodes that penetrate the first die;   first pads at a top surface of the first die and coupled to the through electrodes;   a second die on the first die;   second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die;   connection terminals that connect the first pads to the second pads; and   a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals,   wherein a first width of each of the first pads in the central region is greater than a second width of each of the first pads in the peripheral region,   wherein each of the connection terminals includes a convex portion at a lateral surface thereof, which protrudes beyond a lateral surface of a respective first pad and a lateral surface of a respective second pad, the convex portion protruding in a direction away from a center of the first die, and   wherein protruding distances of the convex portions increase in a direction from the center of the first die toward an outside of the first die.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the first width of each of the first pads on the central region is about 1.01 times to about 1.5 times the second width of each of the first pads on the peripheral region. 
     
     
         3 . The semiconductor package of  claim 1 , wherein a first ratio of the first width in a first direction to an arrangement period of the first pads on the central region in the first direction is greater than a second ratio of the second width in the first direction to an arrangement period of the first pads on the peripheral region in the first direction. 
     
     
         4 . The semiconductor package of  claim 1 , wherein an area of each of the first pads on the central region is greater than an area of each of the first pads on the peripheral region. 
     
     
         5 . The semiconductor package of  claim 1 , wherein:
 each of the connection terminals includes a concave portion that is recessed from the lateral surface of a respective first pad and the lateral surface of a respective second pad,   the convex portion is on a first side of the connection terminal, the first side being directed toward the outside of the first die, and   the concave portion is a second side of the connection terminal, the second side being directed toward an inside of the first die.   
     
     
         6 . The semiconductor package of  claim 5 , wherein recessed depths of the concave portions increase in a direction from the center of the first die toward the outside of the first die. 
     
     
         7 . The semiconductor package of  claim 1 , further comprising:
 a substrate;   a plurality of substrate terminals on a bottom surface of the first die and connecting the first die to the substrate; and   a molding layer on the substrate and covering the first die and the second die.   
     
     
         8 . A semiconductor package, comprising:
 a first die;   a plurality of second dies stacked on the first die, each of the second dies including first pads, second pads, a plurality of third pads, and fourth pads, the first pads and the second pads being on a top surface of the respective second die, and the third pads and the fourth pads being on a bottom surface of the respective second die;   for each pair of adjacent second dies, first connection terminals, which connect the first pads of a lower second die of the pair of adjacent second dies to the third pads of an upper second die of the pair of adjacent second dies, the first pads and the third pads vertically overlapping each other between the pair of adjacent second dies;   for each pair of adjacent second dies, second connection terminals, which connect the second pads of a lower second die of the pair of adjacent second dies to the fourth pads of an upper second die of the pair of adjacent second dies, the second pads and the fourth pads vertically overlapping each other between the pair of adjacent second dies;   for each pair of adjacent second dies, a dielectric layer that fills a space between the pair of adjacent second dies; and   a plurality of external terminals below the first die and connecting the first die to a substrate,   wherein the first and third pads are in a central region of the second dies,   wherein the second and fourth pads are in a peripheral region of the second dies that is outside of the central region, and   wherein a first ratio of the maximum width of each first pad in a first horizontal direction to an arrangement period of the first pads in the first horizontal direction is greater than a second ratio of the maximum width of each second pad in the first horizontal direction to an arrangement period of the second pads in the first horizontal direction.   
     
     
         9 . The semiconductor package of  claim 8 , wherein the maximum width of each first pad in the first horizontal direction and the maximum width of each third pad in the first horizontal direction are greater than each of the maximum width of each second pad in the first horizontal direction and the maximum width of each fourth pad in the first horizontal direction. 
     
     
         10 . The semiconductor package of  claim 9 , wherein the maximum width of each first pad in the first horizontal direction and the maximum width of each third pad in the first horizontal direction are about 1.01 times to about 1.5 times the maximum width of each second pad in the first horizontal direction and the maximum width of each fourth pad in the first horizontal direction. 
     
     
         11 . The semiconductor package of  claim 8 , wherein the arrangement period of the first pads is the same as the arrangement period of the second pads. 
     
     
         12 . The semiconductor package of  claim 8 , wherein the first ratio is about 1.01 times to about 1.5 times the second ratio. 
     
     
         13 . The semiconductor package of  claim 8 , wherein:
 each of the first connection terminals includes a first convex portion that protrudes beyond lateral surfaces of respective first and third pads, the first convex portion being on one side of the first connection terminal, the one side of the first connection terminal being directed toward an outside of the first die,   each of the second connection terminals includes a second convex portion that protrudes beyond lateral surfaces of respective second and fourth pads, the second convex portion being on one side of the second connection terminal, the one side of the second connection terminal being directed toward the outside of the first die, and   the maximum protruding distance of each second convex portion in a direction perpendicular to the lateral surfaces of respective second and fourth pads is greater than a protruding distance of each first convex portion in a direction perpendicular to the lateral surfaces of respective first and third pads.   
     
     
         14 . The semiconductor package of  claim 13 , wherein:
 each first convex portion is spaced apart from an adjacent first connection terminal, and   each second convex portion is spaced apart from an adjacent second connection terminal.   
     
     
         15 . The semiconductor package of  claim 8 , wherein:
 each of the first connection terminals includes a first concave portion that is recessed from lateral surfaces of the first and third pads, the first concave portion being on a first side of the first connection terminal, the first side of the first connection terminal being directed toward an inside of the first die,   each of the second connection terminals includes a second concave portion that is recessed from lateral surfaces of the second and fourth pads, the second concave portion being on a first side of the second connection terminal, the first side of the second connection terminal being directed toward the inside of the first die, and   a recessed depth of each second concave portion is greater than a recessed depth of each first concave portion.   
     
     
         16 . A semiconductor package, comprising:
 a substrate;   a plurality of dies stacked on the substrate, each die of the plurality of dies including first pads on a top surface of the die and second pads on a bottom surface of the die;   connection terminals that connect the first pads to the second pads; and   a dielectric layer that fills a space between the dies and surrounds the connection terminals,   wherein the dies have a central region and a peripheral region that surrounds the central region,   wherein a first area of each of the first pads in the central region is greater than a second area of each of the first pads in the peripheral region, and   wherein each of the connection terminals includes a convex portion on one side of the connection terminal and no convex portion on a second, opposite side of the connection terminal, the one side being directed toward an outside of the die.   
     
     
         17 . The semiconductor package of  claim 16 , wherein the maximum width in a first direction of each of the first pads in the central region is greater than the maximum width in the first direction of each of the first pads in the peripheral region. 
     
     
         18 . The semiconductor package of  claim 17 , wherein the maximum width in the first direction of each of the first pads in the central region is about 1.01 times to about 1.5 times the maximum width in the first direction of each of the first pads in the peripheral region. 
     
     
         19 . The semiconductor package of  claim 16 , wherein a first ratio of the maximum width in a first direction of each of the first pads on the central region to an arrangement period in the first direction of the first pads on the central region is greater than a second ratio of the maximum width in the first direction of each of the first pads on the peripheral region to an arrangement period in the first direction of the first pads on the peripheral region. 
     
     
         20 . The semiconductor package of  claim 16 , wherein protruding distances of the convex portions increase in a direction from a center of the dies toward an outside of the dies.