Semiconductor package

Abstract

A semiconductor package includes a package substrate, a power module on a first surface of the package substrate, a connector on the first surface of the package substrate, the connector being horizontally spaced apart from the power module, a first semiconductor chip on a second surface of the package substrate opposite to the first surface, and a first heat radiator on the second surface of the package substrate, the first heat radiator covering the first semiconductor chip. The first semiconductor chip vertically overlaps the power module, and the first semiconductor chip is electrically connected through the package substrate to the power module.

What is claimed is: 
     
         1 . A semiconductor package comprising:
 a package substrate;   a power module on a first surface of the package substrate;   a connector on the first surface of the package substrate, the connector being horizontally spaced apart from the power module;   a first semiconductor chip on a second surface of the package substrate opposite to the first surface;   a first heat radiator on the second surface of the package substrate, the first heat radiator covering the first semiconductor chip;   a connection substrate on the second surface of the package substrate and having an opening that penetrates the connection substrate, the first semiconductor chip being in the opening; and   a dielectric layer in the opening and filling a space between the connection substrate and the first semiconductor chip,   wherein the first heat radiator is attached to one surface of the connection substrate and to a rear surface of the first semiconductor chip,   wherein at least a portion of the first semiconductor chip vertically overlaps the power module, and   wherein the first semiconductor chip is electrically connected through the package substrate to the power module.   
     
     
         2 . The semiconductor package of  claim 1 , further comprising:
 a through electrode that vertically penetrates the dielectric layer and is coupled to the package substrate,   wherein the rear surface of the first semiconductor chip is exposed on one surface of the dielectric layer, and   wherein the first heat radiator is attached to the rear surface of the first semiconductor chip.   
     
     
         3 . The semiconductor package of  claim 1 , wherein each of the first semiconductor chip includes:
 a first interposer on the package substrate;   a die stack on the first interposer and including a plurality of vertically stacked first dies; and   a second die on the first interposer, the second die being horizontally spaced apart from the die stack.   
     
     
         4 . The semiconductor package of  claim 1 , wherein the semiconductor package is connected to an external device through a cable coupled to the connector. 
     
     
         5 . The semiconductor package of  claim 1 , wherein
 the power module and the connector are flip-chip mounted on the first surface of the package substrate, and   the first semiconductor chip is in contact with the second surface of the package substrate and chip pads of the first semiconductor chip are directly connected to substrate pads of the package substrate.   
     
     
         6 . The semiconductor package of  claim 1 , further comprising a fixing member on one side of the first semiconductor chip, the fixing member penetrating the first heat radiator and the package substrate,
 wherein the first heat radiator is fixed to the package substrate by the fixing member.   
     
     
         7 . The semiconductor package of  claim 1 , further comprising a module socket on the first surface of the package substrate,
 wherein the power module is connected to the module socket.   
     
     
         8 . A semiconductor package comprising:
 a package substrate having a central region and a peripheral region on opposite sides of the central region, the peripheral region being at an outer edge of the package substrate;   a power module on the central region and on a first surface of the package substrate;   a heat radiator on a second surface of the package substrate;   a first connection substrate between the package substrate and the heat radiator and having a first opening that penetrates the first connection substrate;   a first semiconductor chip on the second surface of the package substrate and in the first opening of the first connection substrate; and   a first dielectric layer in the first opening and filling a space between the first connection substrate and the first semiconductor chip,   wherein an active surface of the first semiconductor chip is in contact with the package substrate, and   wherein the first semiconductor chip is electrically connected through the package substrate to the power module.   
     
     
         9 . The semiconductor package of  claim 8 , further comprising a connector on the peripheral region and on the first surface of the package substrate, the connector being horizontally spaced apart from the power module,
 wherein the semiconductor package is connected to an external device through a cable coupled to the connector.   
     
     
         10 . The semiconductor package of  claim 9 , further comprising a first interposer on the first surface of the package substrate,
 wherein the connector is electrically connected through the first interposer to the package substrate.   
     
     
         11 . The semiconductor package of  claim 8 , wherein the first semiconductor chip vertically overlaps the power module. 
     
     
         12 . The semiconductor package of  claim 8 , further comprising:
 a wiring layer between the first connection substrate and the heat radiator;   a second connection substrate between the wiring layer and the heat radiator and having a second opening that penetrates the second connection substrate;   a second semiconductor chip on the wiring layer and in the second opening of the second connection substrate; and   a second dielectric layer in the second opening and filling a space between the second connection substrate and the second semiconductor chip,   wherein the heat radiator is attached to a rear surface of the second semiconductor chip.   
     
     
         13 . The semiconductor package of  claim 12 , wherein
 the first connection substrate includes a conductive pattern that connects the package substrate to the wiring layer, the conductive pattern being in a first region of the first connection substrate, and   the first connection substrate further includes a plurality of passive elements on a second region of the first connection substrate that is spaced apart from the first region.   
     
     
         14 . The semiconductor package of  claim 8 , wherein
 the power module is mounted on the package substrate through a connection terminal between the power module and the package substrate, and   a plurality of chip pads of the first semiconductor chip are directly connected to a plurality of substrate pads of the package substrate.   
     
     
         15 . A semiconductor package comprising:
 a package substrate having a central region and a peripheral region on opposite sides of the central region, the peripheral region being at an outer edge of the package substrate;   a power module on the central region and on a first surface of the package substrate;   a connector on the peripheral region and on the first surface of the package substrate;   a first semiconductor chip on a second surface of the package substrate;   a connection substrate on the second surface of the package substrate and having an opening that penetrates the connection substrate, the first semiconductor chip being in the opening;   a first dielectric layer in the opening and filling a space between the connection substrate and surrounding the first semiconductor chip; and   a first heat radiator attached to one surface of the connection substrate and to a rear surface of the first semiconductor chip,   wherein the first semiconductor chip includes:
 a first interposer on the package substrate; 
 a die stack on the first interposer and including a plurality of vertically stacked first dies; 
 a second die on the first interposer and horizontally spaced apart from the die stack; and 
 a molding layer on the first interposer and surrounding the die stack and the second die, the molding layer exposing a top surface of the die stack, and 
   wherein the semiconductor package is connected to an external device through a cable coupled to the connector.