Multigate device structure with engineered gate

Abstract

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a fin region formed on a substrate, wherein the fin region includes multiple channels vertically stacked on the substrate; a gate stack disposed on the fin region, wherein the gate stack is wrapping around each of the multiple channels and includes gate extensions being extending laterally to be overlapped with inner spacers; and a pair of source/drain (S/D) features formed on the fin region, interposed by the gate stack, and connected with the multiple channels.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a fin region formed on a substrate, wherein the fin region includes multiple channels vertically stacked on the substrate;   a gate stack disposed on the fin region, wherein the gate stack is wrapping around each of the multiple channels, and wherein the gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer;   a pair of source/drain (S/D) features formed on the fin region, interposed by the gate stack, and connected with the multiple channels; and   inner spacers disposed on sidewalls of the pair of S/D features, wherein the gate stack includes gate extensions that overlapped with the inner spacers.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein one of the gate extensions laterally extends on a top surface of one of the channels to be partially overlapped with the inner spacers. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein one of the gate extensions laterally extends on a bottom surface of the one of the channels to be partially overlapped with the inner spacers. 
     
     
         4 . The semiconductor structure of  claim 1 , further comprising
 gate spacers disposed on sidewalls of the gate stack, each laterally spanning a first dimension L1; and   the inner spacers directly underlying the gate spacers and disposed on sidewalls of the S/D features, wherein each of the gate extensions of the gate stack laterally spans a second dimension L2 being less than the first dimension L1.   
     
     
         5 . The semiconductor structure of  claim 4 , wherein a ratio L2/L1 is less than 50%. 
     
     
         6 . The semiconductor structure of  claim 5 , wherein the ratio L2/L1 ranges between 10% and 30%. 
     
     
         7 . The semiconductor structure of  claim 4 , wherein
 each of the inner spacers vertically spans a third dimension L3; and   the each of the gate extensions of the gate stack vertically spans a fourth dimension L4 being less than the third dimension L3.   
     
     
         8 . The semiconductor structure of  claim 7 , wherein a ratio L4/L3 is less than 30%. 
     
     
         9 . The semiconductor structure of  claim 8 , wherein the ratio L4/L3 ranges between 10% and 20%. 
     
     
         10 . The semiconductor structure of  claim 4 , wherein the gate stack laterally extends below a bottommost inner spacer of the inner spacers and directly disposed on the substrate. 
     
     
         11 . The semiconductor structure of  claim 4 , wherein
 each of the channels includes a first segment directly underlying the gate stack, and a second segment directly underlying the gate spacers and contacting one of the S/D features;   the first segment vertically spans a first dimension D1; and   the second segment vertically spans a second dimension D2 being greater than the first dimension D1.   
     
     
         12 . The semiconductor structure of  claim 11 , wherein a ratio D1/D2 ranges between 30% and 40%. 
     
     
         13 . A semiconductor structure, comprising:
 a fin region formed on a substrate, wherein the fin region includes multiple channels vertically stacked on the substrate;   a gate stack disposed on the fin region, wrapping around each of the multiple channels, wherein the gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer;   gate spacers disposed on sidewalls of the gate stack;   source/drain (S/D) features formed on the fin region, interposed by the gate stack, and connected with the multiple channels; and   inner spacers disposed on sidewalls of the S/D features and underlying the gate spacers, wherein the gate stack is laterally extending to partially wrap around the inner spacers.   
     
     
         14 . The semiconductor structure of  claim 13 , wherein
 each of the gate spacers laterally spans a first dimension L1;   each of expended portions of the gate stack laterally spans a second dimension L2 being less than the first dimension L1;   each of the channels includes a first segment directly underlying the gate stack, and a second segment directly underlying the gate spacers and contacting one of the S/D features;   the first segment vertically spans a first dimension D1; and   the second segment vertically spans a second dimension D2 being greater than the first dimension D1.   
     
     
         15 . The semiconductor structure of  claim 13 , wherein the gate stack laterally extends below a bottommost inner spacer of the inner spacers and directly disposed on the substrate. 
     
     
         16 . A semiconductor structure, comprising:
 a fin region formed on a substrate, wherein the fin region includes multiple channels vertically stacked on the substrate;   a gate stack disposed on the fin region, wherein the gate stack is wrapping around each of the multiple channels, and wherein the gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer;   a pair of source/drain (S/D) features formed on the fin region, interposed by the gate stack, and contacting the each of the multiple channels; and   inner spacers disposed on sidewalls of the pair of S/D features, wherein the gate stack includes gate extensions that are overlapped with the inner spacers, and wherein one of the gate extensions laterally extends on a top surface of one of the channels to be overlapped with the inner spacers.   
     
     
         17 . The semiconductor structure of  claim 16 , wherein one of the gate extensions laterally extends on a bottom surface of the one of the channels to be partially overlapped with the inner spacers. 
     
     
         18 . The semiconductor structure of  claim 16 , further comprising
 gate spacers disposed on sidewalls of the gate stack, each laterally spanning a first dimension L1;   the inner spacers directly underlying the gate spacers and disposed on sidewalls of the S/D features, wherein each of the gate extensions of the gate stack laterally spans a second dimension L2 being less than the first dimension L1;   each of the inner spacers vertically spans a third dimension L3; and   the each of the gate extensions of the gate stack vertically spans a fourth dimension L4 being less than the third dimension L3.   
     
     
         19 . The semiconductor structure of  claim 18 , wherein
 each of the channels includes a first segment directly underlying the gate stack, and a second segment directly underlying the gate spacers and contacting one of the S/D features;   the first segment vertically spans a first dimension D1; and   the second segment vertically spans a second dimension D2 being greater than the first dimension D1.   
     
     
         20 . The semiconductor structure of  claim 16 , wherein the gate stack laterally extends below a bottommost inner spacer of the inner spacers and directly disposed on the substrate.