Memory structure and method of forming thereof

Abstract

A memory structure includes a substrate, an isolation area, a plurality of active areas and a first word line. The isolation area and the active areas are formed on the substrate. The isolation area surrounds the active areas, and the isolation area comprises an isolation structure formed in an isolation trench recessed in the isolation area. The first word line is formed across a first active area of the active areas and the isolation area. The first word line has a first width in the first active area and a second width in the isolation area. The first width is less than the second width.

What is claimed is: 
     
         1 . A memory structure, comprising:
 a substrate;   an isolation area and a plurality of active areas, formed on the substrate, wherein the isolation area surrounds the active areas, the isolation area comprises an isolation structure formed in an isolation trench recessed in the isolation area, and a top surface of the isolation structure is lower than top surfaces of the active areas;   a first word line formed across a first active area of the active areas and the isolation area, wherein the first word line has a first width in the first active area and a second width in the isolation area, and the first width is less than the second width, a topmost surface of the isolation structure is lower than a top surface of the first word line, and a level of the topmost surface of the isolation structure is between a level of the top surface of the first word line and a level of a lowest point of the first word line in a cross-sectional view; and   a mask layer formed in the isolation trench and upon the top surface of the isolation structure, wherein the mask layer laterally surrounds the first word line in the isolation area, and a top surface of the mask layer is coplanar with the top surface of the first active area and a top surface of the first word line.   
     
     
         2 . The memory structure of  claim 1 , further comprising:
 a second word line formed across the isolation area and the first active area, wherein the second word line has the first width in the first active area and the second width in the isolation area; and   a bit line structure formed on the first active area and located at a portion of the first active area between the first word line and the second word line.   
     
     
         3 . The memory structure of  claim 2 , wherein the portion of the first active area between the first word line and the second word line, the first word line and a portion of the first active area between the first word line and the isolation area form a first transistor, the portion of the first active area between the first word line and the second word line, and the second word line and a portion of the first active area between the second word line and the isolation area form a second transistor. 
     
     
         4 . The memory structure of  claim 1 , further comprising:
 a third word line formed across the isolation area and a second active area of the active areas, wherein the third word line has the first width in the second active area and the second width in the isolation area; and   a capacitor structure formed on the first active area and between the first word line and the third word line.   
     
     
         5 . The memory structure of  claim 1 , wherein the first word line is formed within a first word line trench across the first active area and the isolation area, the first word line comprises:
 a gate dielectric conformally formed in the first word line trench;   a gate structure formed on the gate dielectric; and   a dielectric layer being formed in the first word line trench and covering the gate structure.   
     
     
         6 . The memory structure of  claim 5 , wherein a top surface of the isolation structure is lower than a top surface of the dielectric layer. 
     
     
         7 . A memory structure, comprising:
 a substrate having a plurality of active areas and an isolation area surrounding the active areas, wherein the isolation area comprises an isolation structure recessed from a top surface of the substrate, wherein a top surface of the isolation structure is lower than top surfaces of the active areas;   a first word line formed across a first active area of the active areas and the isolation structure of the isolation area, wherein a topmost surface of the isolation structure is lower than a top surface of the first word line, and a level of the topmost surface of the isolation structure is between a level of the top surface of the first word line and a level of a lowest point of the first word line in a cross-sectional view; and   a mask layer formed in an isolation trench in the isolation area and upon the top surface of the isolation structure, wherein the mask layer laterally surrounds the first word line in the isolation area, and a top surface of the mask layer is coplanar with the top surface of the first active area and a top surface of the first word line.   
     
     
         8 . The memory structure of  claim 7 , wherein the first word line has a first width in the first active area and a second width in the isolation area, and the first width is less than the second width. 
     
     
         9 . The memory structure of  claim 8 , wherein the first word line is extended along a first direction different from a second direction in which the active areas are extended, and first sections with the first width and second sections with the second width of the first word line are alternately arranged along the first direction. 
     
     
         10 . The memory structure of  claim 8 , further comprising:
 a second word line formed across the isolation area and the first active area, wherein the second word line has the first width in the first active area and the second width in the isolation area; and   a bit line structure formed on the first active area and located at a portion of the first active area between the first word line and the second word line.   
     
     
         11 . The memory structure of  claim 8 , further comprising:
 a third word line formed across the isolation area and a second active area of the active areas, wherein the third word line has the first width in the second active area and the second width in the isolation area; and   a capacitor structure formed on the first active area and between the first word line and the third word line.