Semiconductor package and manufacturing method thereof

Abstract

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first device die; a second device die, stacked on the first device die; and first electrical connectors and second electrical connectors, disposed in between the first and second device dies. A first pitch between the first electrical connectors is greater than a second pitch between the second electrical connectors. The first and second electrical connectors respectively comprise a solder joint and first metallic layers lying at opposite sides of the solder joint and formed of a first metallic material. Each of the second electrical connectors further comprises at least one second metallic layer formed of a second metallic material.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a first device die;   a second device die, stacked on the first device die; and   first electrical connectors and second electrical connectors, disposed in between the first and second device dies, wherein a first pitch between the first electrical connectors is greater than a second pitch between the second electrical connectors, the first and second electrical connectors respectively comprise a solder joint and first metallic layers lying at opposite sides of the solder joint and formed of a first metallic material, and each of the second electrical connectors further comprises at least one second metallic layer formed of a second metallic material.   
     
     
         2 . The semiconductor package according to  claim 1 , wherein the at least one second metallic layer in each second electrical connector comprise two second metallic layers each lying between adjacent ones of the first metallic layers at one side of the solder joint, and the first metallic layers in each of the second electrical connectors are respectively thinner than each first metallic layer in each of the first electrical connectors. 
     
     
         3 . The semiconductor package according to  claim 1 , wherein the at least one second metallic layer in each second electrical connector comprise a single second metallic layer lying between adjacent ones of the first metallic layers at a side of the solder joint, and the first metallic layers at the side of the solder joint in each of the second electrical connectors are respectively thinner than each first metallic layer in each of the first electrical connectors. 
     
     
         4 . The semiconductor package according to  claim 1 , wherein the first metallic material comprises copper, and the second metallic material comprises nickel, cobalt, iron or combinations thereof. 
     
     
         5 . The semiconductor package according to  claim 1 , wherein each of the first and second electrical connectors further comprise seed layers at opposite ends. 
     
     
         6 . The semiconductor package according to  claim 1 , further comprising:
 a first polymer layer, lining along a surface of the first device die; and   a second polymer layer, lining along a surface of the second device die, and bonded with the first polymer layer, wherein the first and second electrical connectors extend through the first and second polymer layers.   
     
     
         7 . The semiconductor package according to  claim 1 , further comprising:
 an underfill, filled in between the first and second device dies, and laterally surrounding the first and second electrical connectors.   
     
     
         8 . The semiconductor package according to  claim 1 , wherein each of the first and second electrical connectors has an upper half and a lower half narrower than the upper half. 
     
     
         9 . The semiconductor package according to  claim 1 , wherein a first critical width of each first electrical connector is greater than a second critical width of each second electrical connector. 
     
     
         10 . The semiconductor package according to  claim 1 , wherein the second electrical connectors are arranged around an array of the first electrical connectors. 
     
     
         11 . The semiconductor package according to  claim 1 , wherein the second electrical connectors are surrounded by the first electrical connectors. 
     
     
         12 . A semiconductor package, comprising:
 a first device die;   a second device die, stacked on the first device die;   a first polymer layer, disposed on a surface of the first device die;   a second polymer layer, disposed on a surface of the second device die, and bonded with the first polymer layer;   first electrical connectors and second electrical connectors, extending through the first and second polymer layers, wherein the first and second electrical connectors respectively comprise a solder joint and first metallic layers lying at opposite sides of the solder joint and formed of a first metallic material, and each of the second electrical connectors further comprises at least one second metallic layer formed of a second metallic material;   a first encapsulant, disposed on the first device die, and laterally encapsulating the second device die; and   a second encapsulant, laterally surrounding the first encapsulant and the first device die.   
     
     
         13 . The semiconductor package according to  claim 12 , wherein the first device die comprises:
 a semiconductor substrate;   front metallization layers, lying along an active side of the semiconductor substrate;   back metallization layers, lying along a back side of the semiconductor substrate; and   through substrate vias, penetrating through the semiconductor substrate,   wherein the first and second electrical connectors stand on the back metallization layers.   
     
     
         14 . The semiconductor package according to  claim 12 , wherein the first device die comprises:
 a semiconductor substrate;   front metallization layers, lying along an active side of the semiconductor substrate; and   through substrate vias, penetrating through at least a portion of the semiconductor substrate,   wherein the first and second electrical connectors are located on the front metallization layers.   
     
     
         15 . The semiconductor package according to  claim 12 , further comprising:
 a first redistribution structure, lying below the second encapsulant and the first device die; and   conductive bumps, disposed at a bottom side of the first redistribution structure.   
     
     
         16 . The semiconductor package according to  claim 15 , further comprising:
 through encapsulant vias, standing on the first redistribution structure around the first encapsulant and the first device die, and penetrating through at least a portion of the second encapsulant; and   a second redistribution structure, lying on the second encapsulant, the through encapsulant vias, the first encapsulant and the second device die.   
     
     
         17 . A semiconductor package, comprising:
 a first package component;   a second package component, vertically spaced apart from the first package component; and   first electrical connectors and second electrical connectors, disposed in between the first and second package components and connecting the first and second package components with each other, wherein a first critical width of each first electrical connector is greater than a second critical width of each second electrical connector, the first and second electrical connectors respectively comprise a solder joint and first metallic layers lying at opposite sides of the solder joint and formed of a first metallic material, and each of the second electrical connectors further comprises at least one second metallic layer formed of a second metallic material.   
     
     
         18 . The semiconductor package according to  claim 17 , wherein a first pitch between the first electrical connectors is greater than a second pitch between the second electrical connectors. 
     
     
         19 . The semiconductor package according to  claim 17 , wherein the first package component is a device die, and the second package component is another device die, an interposer, a bridge die or a redistribution structure. 
     
     
         20 . The semiconductor package according to  claim 17 , wherein the first package component is a bridge die or a passive die, and the second package component is a redistribution structure.