Manufacturing method for a power semiconductor device and power semiconductor device

Abstract

The present disclosure relates to a manufacturing method for a power semiconductor device ( 1, 40 ), comprising: forming multiple growth templates on a carrier substrate ( 2 ), comprising at least a first plurality of hollow growth templates ( 18 ) and a second plurality of hollow growth templates ( 28 ); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each one of the first hollow growth templates ( 18 ), thereby forming a corresponding plurality of first semiconductor structures ( 5 ) of a first type, in particular n+/p−/n−/n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each one of the second hollow growth templates ( 28 ), thereby forming a corresponding plurality of second semiconductor structures ( 6 ) of a second type, in particular n+/n−/p−/n+ structures. The disclosure further relates to a power semiconductor device ( 1, 40 ) comprising a carrier substrate ( 2 ), at least one dielectric layer ( 4, 27, 31 ), a plurality of first semiconductor structures ( 5 ) of a first type, and a plurality of second semiconductor structures ( 6 ) of a second type formed within the at least one dielectric layer ( 4, 27, 31 ).

The invention claimed is: 
     
         1 . A manufacturing method for a power semiconductor device, comprising:
 forming multiple growth templates on a carrier substrate, comprising at least a first plurality of hollow growth templates and a second plurality of hollow growth templates;   selectively growing a first sequence of differently doped wide bandgap, WBG, semiconductor material in each one of the first hollow growth templates, thereby forming a corresponding plurality of first semiconductor structures of a first type;   forming a plurality of first gate structures, each one of the first gate structures surrounding at least a channel area of a corresponding one of the plurality of first semiconductor structures;   forming at least one dielectric layer, wherein the first gate structures are buried in the at least one dielectric layer;   selectively growing a second sequence of differently doped WBG semiconductor material in each one of the second hollow growth templates, wherein the second sequence differs from the first sequence, thereby forming a corresponding plurality of second semiconductor structures of a different, second type; and   forming a plurality of second gate structures, each one of the second gate structures surrounding at least a channel area of a corresponding one of the plurality of second semiconductor structures, wherein the second gate structures are formed at closer to an upper surface of the at least one dielectric layer than the first gate structures, such that the first gate structures and the second gate structures vertically offset with respect to each other, wherein the plurality of first semiconductor structures are connected in parallel to allow for an increase in current density, and wherein the plurality of first semiconductor structures of the first type and the plurality of second semiconductor structures of the second type are connected in sequence to form a half-bridge.   
     
     
         2 . The method of  claim 1 , wherein in the step of forming multiple growth templates, an array of vertically oriented growth templates is formed, wherein each one of the vertically oriented growth templates extends in a direction perpendicular to a main surface of the carrier substrate. 
     
     
         3 . The method of  claim 1 , wherein the step of forming multiple growth templates comprises:
 depositing and structuring a sacrificial material, in particular amorphous silicon, on the carrier substrate;   covering the structured sacrificial material with a layer of dielectric material; and   selectively removing the sacrificial material surrounded by the dielectric material to form the first and second plurality of hollow growth templates.   
     
     
         4 . The method of  claim 1 , wherein initially upper ends of the multiple growth templates are sealed, and the method further comprises:
 before growing the first sequence of differently doped WBG semiconductor material, opening only the upper ends of a first subset of the first plurality of hollow multiple growth templates;   after growing the first sequence of differently doped WBG semiconductor materials, re-sealing the upper ends of the first subset; and   before growing the second sequence of differently doped WBG semiconductor material, opening only the upper ends a second subset of the second plurality of growth templates.   
     
     
         5 . The method of  claim 1 , wherein the first and second sequence of differently doped WBG semiconductor material is selectively grown by chemical vapor deposition, CVD, using different dopant profiles. 
     
     
         6 . The method of  claim 1 , wherein the first hollow growth templates and/or the second hollow growth templates extend to a crystalline material of the carrier substrate, and, in steps of selectively growing, the crystalline material acts as a seed area for the WBG semiconductor material. 
     
     
         7 . The method of  claim 1 , wherein:
 in the step of selectively growing the first sequence of differently doped WBG semiconductor material in each one of the first hollow growth templates, a corresponding plurality of n+/p−/n−/n+ semiconductor structures is formed from bottom to top starting from the carrier substrate; and   in the step of selectively growing the second sequence of differently doped WBG semiconductor material in each one of the second hollow growth templates, a corresponding plurality of n+/n−/p−/n+ semiconductor structures is formed from bottom to top starting from the carrier substrate.   
     
     
         8 . The method of  claim 1 , further comprising:
 forming a first top side contact, in particular a positive DC terminal of a half-bridge structure, electrically connected to at least a subgroup of the plurality of first semiconductor structures;   forming a second top side contact, in particular a negative DC terminal of a half-bridge structure, electrically connected to at least a subgroup of the plurality of second semiconductor structures; and/or   forming a bottom contact, in particular an AC terminal of a half-bridge structure, electrically connected to at least a subgroup of the plurality of first semiconductor structures and a subgroup of the plurality of second semiconductor structures.   
     
     
         9 . A power semiconductor device, comprising:
 a carrier substrate comprising at least one bottom contact;   at least one dielectric layer formed on the carrier substrate;   a plurality of first semiconductor structures of a first type formed within the at least one dielectric layer, each one of the first semiconductor structures electrically connected to the bottom contact and comprising a first sequence of differently doped sublayers of a wide bandgap, WBG, semiconductor material;   a plurality of buried first gate structures arranged within the at least one dielectric layer, each one of the first gate structures surrounding a channel area of a corresponding one of the first semiconductor structures;   a plurality of second semiconductor structures of a different, second type formed within the at least one dielectric layer, each one of the second semiconductor structures electrically connected to the bottom contact and comprising a second sequence of differently doped sublayers of the WBG semiconductor material, wherein the second sequence differs from the first sequence;   a plurality of second gate structures arranged at closer to an upper surface of the at least one dielectric layer than the first gate structures, each one of the second gate structures surrounding a channel area of a corresponding one of the second semiconductor structures, wherein the first gate structures and the second gate structures are vertically offset with respect to each other,   a first top side contact arranged on the upper surface of the at least one dielectric layer, the first top side contact electrically connecting at least a subgroup of the plurality of first semiconductor structures; and   a second top side contact arranged on the upper surface of the at least one dielectric layer, the second top side contact electrically connecting at least a subgroup of the plurality of second semiconductor structures, wherein the first semiconductor structures of the first type are n+/p−/n−/n+ semiconductor structures from bottom to top starting from the carrier substrate, and the second semiconductor structures of the second type are n+/n−/p−/n+ semiconductor structures from bottom to top starting from the carrier substrate.   
     
     
         10 . The device of  claim 9 , wherein:
 the at least one dielectric layer comprises an array of vertically oriented growth templates extending in a direction perpendicular to a main surface of the carrier substrate;   the first semiconductor structures are nanowire structures selectively grown in a first subset of the array of vertically oriented growth templates; and   the second semiconductor structures are nanowire structures selectively grown in a second subset of the array of vertically oriented growth templates.   
     
     
         11 . The device of  claim 10 , wherein
 the nanowire structures have a diameter of 10 nm to 10 μm;   the nanowire structures have a length of 1 μm to 100 μm, and/or   the at least one dielectric layer has a thickness of 1 μm to 100 μm.   
     
     
         12 . The device of  claim 9 , wherein
 the carrier substrate comprises a layer made from silicon, Si, and/or polycrystalline silicon carbide, poly-SiC;   the at least one dielectric layer comprises a dioxide, in particular silicon dioxide, SiO2, or aluminum oxide, Al2O3; and/or   the WBG semiconductor material comprises silicon carbide, SiC, in particular one of 4H—SiC, 6H—SiC or 3C—SiC.   
     
     
         13 . The device of  claim 9 , wherein:
 the plurality of buried first gate structures are configured to form first metal insulator semiconductor field effect transistors, MISFETs, in particular first MOSFETS or AccuFETs; and/or   the plurality of second gate structures are configured to form second MISFETs, in particular second MOSFETs or AccuFETs.   
     
     
         14 . The device of  claim 13 , comprising:
 a half-bridge circuit, wherein the at least one bottom contact corresponds to an AC terminal of the half-bridge circuit, the first top side contact corresponds to a positive DC terminal of the half-bridge circuit, the second top side contact corresponds to a negative DC terminal of a half-bridge circuit, the buried first gate structures are connected in parallel to a first gate contact to selectively switch a first branch of the half-bridge circuit, in particular a high side of the half-bridge circuit, and the second gate structures are connected in parallel to a second gate contact to selectively switch a second branch of the half-bridge circuit, in particular a low side of the half-bridge circuit; or   a full-bridge circuit, wherein the buried gate structures corresponding to a first subset of the first semiconductor structures are connected in parallel to a first gate contact to selectively switch a first branch of the full-bridge circuit, the buried gate structures corresponding to a second subset of the first semiconductor structures are connected in parallel to a second gate contact to selectively switch a second branch of the full-bridge circuit, the second gate structures corresponding to a first subset of the second semiconductor structures are connected in parallel to a third gate contact to selectively switch a third branch of the full-bridge circuit, and the further gate structures corresponding to a second subset of the second semiconductor structures are connected in parallel to a fourth gate contact to selectively switch a fourth branch of the full-bridge circuit.