ESD protection device

Abstract

Systems and methods for protecting a device from an electrostatic discharge (ESD) event are provided. A resistor-capacitor (RC) trigger circuit and a driver circuit are provided. The RC trigger circuit is configured to provide an ESD protection signal to the driver circuit. A discharge circuit includes a first metal oxide semiconductor (MOS) transistor and a second MOS transistor connected in series between a first voltage potential and a second voltage potential. The driver circuit provides one or more signals for turning the first and second MOS transistors on and off.

What is claimed is: 
     
         1 . An electrostatic discharge (ESD) protection device comprising:
 a driver circuit comprising a first transistor, a fourth transistor and a plurality of branches, wherein the fourth transistor and the plurality of branches are configured to receive a same ESD protection signal; and   a discharge circuit comprising a second transistor and a third transistor, wherein the first transistor has a gate terminal connected to a gate terminal of the second transistor and a source or drain terminal connected to a gate terminal of the third transistor, wherein when an ESD spike is applied to ESD protection device, the ESD protection signal turns the first transistor off and the second transistor on, and wherein a source or drain terminal of the fourth transistor is connected to the source or drain terminal of the first transistor and the gate terminal of the third transistor.   
     
     
         2 . The ESD protection device of  claim 1 , further comprising a trigger circuit configured to generate the ESD protection signal. 
     
     
         3 . The ESD protection device of  claim 2 , wherein the trigger circuit includes a resistance element and a capacitance element. 
     
     
         4 . The ESD protection device of  claim 3 , wherein the capacitance element is implemented by connecting a drain terminal and a source terminal of a transistor together. 
     
     
         5 . The ESD protection device of  claim 3 , wherein the capacitance element is formed by two or more transistors connected in parallel. 
     
     
         6 . The ESD protection device of  claim 2 , wherein an RC time constant of the trigger circuit is in a range of 100 to 900 nanoseconds. 
     
     
         7 . The ESD protection device of  claim 1 , wherein when the second transistor of the discharge circuit is turned off, a leakage current of the discharge circuit is less than or substantially equal to 0.3 μA. 
     
     
         8 . The ESD protection device of  claim 1 , wherein the second transistor of the discharge circuit is an NMOS transistor. 
     
     
         9 . An electrostatic discharge (ESD) protection circuit comprising:
 a first transistor configured to connect a gate terminal of a second transistor to a source or drain terminal of the second transistor;   a third transistor configured to connect a gate terminal of a fourth transistor to a source or drain terminal of the fourth transistor; and   a fifth transistor connected in series with the first transistor, wherein the first transistor has a gate terminal connected to the gate terminal of the fifth transistor, wherein gate terminals of the first, third, and fifth transistors are configured to receive a same ESD protection signal, and at least one of the second and fourth transistors is a PMOS transistor.   
     
     
         10 . The ESD protection circuit of  claim 9 , wherein when the second and fourth transistors are turned off, a leakage current of the second and fourth transistors is less than or equal to 0.3 μA. 
     
     
         11 . The ESD protection circuit of  claim 9 , wherein the second and fourth transistors are a fin field-effect transistor. 
     
     
         12 . The ESD protection circuit of  claim 9 , wherein the second and fourth transistors are connected in series to a ground. 
     
     
         13 . The ESD protection circuit of  claim 9 , wherein both of the second and fourth transistors are PMOS transistors. 
     
     
         14 . The ESD protection circuit of  claim 9 , wherein:
 the second and fourth transistors are connected in series to a voltage potential;   an ESD current flows through the second and fourth transistors when an ESD spike is applied to the voltage potential; and   the second and fourth transistors are turned off when the voltage potential is free of the ESD spike.   
     
     
         15 . A method comprising:
 turning off a first transistor of a discharge circuit of an ESD protection device,
 wherein the ESD protection device further comprises a driver circuit that includes a second transistor, a fourth transistor, and a plurality of branches, and the fourth transistor and the plurality of branches are configured to receive a same ESD protection signal, 
 wherein the first transistor has a gate terminal connected to a gate terminal of the second transistor, the discharge circuit further includes a third transistor, and the second transistor has a source or drain terminal directly connected to a gate terminal of the third transistor, 
 wherein a source or drain terminal of the fourth transistor is connected to the source or drain terminal of the second transistor and the gate terminal of the third transistor; and 
   when the ESD protection signal is received by the branches, turning on the first transistor.   
     
     
         16 . The method of  claim 15 , wherein the ESD protection device further includes a trigger circuit configured to generate the ESD protection signal. 
     
     
         17 . The method of  claim 15 , wherein the first transistor is connected between a first voltage potential and a second voltage potential. 
     
     
         18 . The method of  claim 17 , wherein an ESD current flows from the first voltage potential to the second voltage potential and clamps a voltage between the first voltage potential and the second voltage potential. 
     
     
         19 . The ESD protection circuit of  claim 9 , wherein the third transistor has a source or drain terminal connected to the source or drain terminal of the fourth transistor. 
     
     
         20 . The ESD protection device of  claim 1 , wherein the second and third transistors are NMOS transistors, and the first and fourth transistors are PMOS transistors.