Planar mixed SOI-bulk substrate for microelectronic applications

Abstract

A process for creating a substrate including bulk silicon regions and semiconductor-on-insulator regions. Regions of a surface of a bulk silicon substrate are recessed above regions where it is desired to create buried oxide regions in the substrate. Implant mask regions are formed on the surface of the substrate over regions where it is not desired to create buried oxide regions. Buried oxide regions are formed in the substrate under the recessed regions in the substrate. The implant mask regions are removed, leaving bulk silicon regions between the buried oxide regions

We claim:  
     
         1 . A process for creating a substrate including bulk silicon regions and semiconductor-on-insulator regions, the process comprising: 
 recessing regions of a surface of a bulk silicon substrate above regions where it is desired to create buried oxide regions in the substrate;    forming implant mask regions on the surface of the substrate over regions where it is not desired to create buried oxide regions;    forming buried oxide regions in the substrate under the recessed regions in the substrate; and    removing the implant mask regions, leaving bulk silicon regions between the buried oxide regions.    
     
     
         2 . The process according to    claim 1   , wherein recessing regions of a surface of a bulk silicon substrate comprises: 
 growing a plurality of reverse oxide regions extending into the bulk silicon substrate above regions where it is desired to create buried oxide regions in the substrate; and    stripping the reverse oxide regions, resulting in the recessed regions in the surface of the substrate where the reverse oxide regions are removed.    
     
     
         3 . The process according to    claim 1   , further comprising: 
 providing a planar surface to the substrate prior to forming the implant mask regions.    
     
     
         4 . The process according to    claim 3   , wherein providing the planar surface comprises filling in the recessed regions in the substrate surface prior to forming the implant mask regions.  
     
     
         5 . The process according to    claim 4   , further comprising 
 removing the recess filling material after forming the implant mask regions.    
     
     
         6 . The process according to    claim 3   , wherein filling in the recessed regions comprises depositing a material in the recessed regions.  
     
     
         7 . The process according to    claim 6   , further comprising 
 removing the recess filling material after forming the implant mask regions.    
     
     
         8 . The process according to    claim 4   , wherein the recess filling material is a different material than material utilized to form the implant mask regions.  
     
     
         9 . The process according to    claim 7   , wherein the recess filling material is preferentially etched off prior to forming buried oxide regions in the substrate under the recessed regions in the substrate.  
     
     
         10 . The process according to    claim 1   , further comprising: 
 polishing portions of the substrate surface after removing the implant mask regions.    
     
     
         11 . The process according to    claim 1   , further comprising: 
 forming dislocation filters to prevent the proliferation of dislocations from the buried oxide regions into surrounding bulk substrate regions.    
     
     
         12 . The process according to    claim 1   , wherein forming the buried oxide regions comprises: 
 utilizing a dose of oxygen ions of about 10 16  ions per square centimeter to about 10 18  ions per square centimeter at an energy level of more than about 10 KeV to less than about 1000 KeV; and    annealing the substrate at a temperature of about 1200° C. to about 1350° C.    
     
     
         13 . The process according to    claim 12   , wherein the dose of oxygen ions is about 10 18  ions per square centimeter and the anneal temperature is about 1325° C.  
     
     
         14 . The process according to    claim 1   , further comprising: 
 forming DRAM array elements and associated circuitry in the bulk silicon regions; and    forming high performance logic elements in the semiconductor-on-insulator regions.    
     
     
         15 . The process according to    claim 1   , wherein the semiconductor-on-insulator regions comprise silicon-on-insulator regions.  
     
     
         16 . A semiconductor substrate including bulk silicon and semiconductor-on-insulator regions, comprising: 
 a bulk silicon substrate;    buried oxide regions in the substrate; and    bulk silicon regions between the buried oxide regions;    wherein an upper surface of the substrate is planar.    
     
     
         17 . The semiconductor substrate according to    claim 16   , further comprising: 
 dislocation filters between the buried oxide regions and the bulk substrate regions.    
     
     
         18 . The semiconductor substrate according to    claim 16   , further comprising: 
 DRAM array elements and associated circuitry in the bulk silicon regions; and    high performance logic elements in the semiconductor-on-insulator regions.    
     
     
         19 . The semiconductor substrate according to    claim 16   , wherein the semiconductor-on-insulator regions comprise silicon-on-insulator regions.