Method for lift-off of epitaxially grown semiconductors by electrochemical anodic etching

Abstract

A method is disclosed for separating a semiconductor epitaxial structure from an insulating growth substrate. The method utilizes electrochemical anodic reactions to remove a thin etch layer disposed near the growth interface. The thin etch layer can be an intentional layer made of a material different from the epitaxial structure and/or can include a material with a high defect density. The method can be applied in the fabrication of optoelectronic and electronic devices from III-V materials, in particular gallium-nitride based materials.

We claim:  
     
         1 . A method for selectively freeing an epitaxial film from an electrically insulating growth substrate comprising 
 (a) placing an electrically conductive layer on a surface of the epitaxial film facing away from the insulating substrate to provide an electric contact with the epitaxial film,    (b) placing the epitaxial film having the conductive layer and the insulating substrate in an etching solution, and    (c) applying an electrochemical potential between the epitaxial film and a counter electrode to dissociate an etch layer positioned between the epitaxial film and the insulating substrate to thereby separate the epitaxial film and the insulating substrate from each other.    
     
     
         2 . The method according to  claim 1 , wherein the epitaxial film comprises a III-V semiconductor material.  
     
     
         3 . The method according to  claim 2 , wherein the III-V material comprises a material selected from the group consisting of GaN, AlN, InN and alloys thereof.  
     
     
         4 . The method according to  claim 1 , wherein the etch layer is an n-type layer.  
     
     
         5 . The method according to  claim 1 , wherein the etch layer includes a defect structure having a concentration of defects that is greater than a concentration of defects in the epitaxial film.  
     
     
         6 . The method according to  claim 5 , wherein the etch layer includes a layer grown at a growth temperature that is substantially less than a growth temperature of the epitaxial film.  
     
     
         7 . The method according to  claim 6 , wherein the etch layer comprises a low-temperature (LT) GaN layer.  
     
     
         8 . The method according to  claim 1 , wherein the applied electrochemical potential is greater than the anodization potential of the etch layer and smaller than the anodization potential of the epitaxial film.  
     
     
         9 . The method according to  claim 1 , wherein the insulating growth substrate comprises sapphire.  
     
     
         10 . The method according to  claim 1 , wherein the epitaxial film comprises a semiconductor device structure.  
     
     
         11 . The method according to  claim 10 , wherein the semiconductor device structure comprises at least one n-type layer and at least one p-type layer.  
     
     
         12 . The method according to  claim 11 , wherein the semiconductor device structure is one of a light-emitting diode (LED) or a vertical cavity surface emitting laser (VCSEL).  
     
     
         13 . The method according to  claim 12 , wherein one of the at least one n-type layers is disposed adjacent to the etch layer opposite to the growth substrate.  
     
     
         14 . The method according to  claim 12 , wherein the electrochemical potential is applied between one of the at least one n-type layers and p-type layers and the counter electrode, and further including applying a second potential between an n-type layer and a p-type layer so as to forward bias the n-type layer and p-type layer to cause light emission.  
     
     
         15 . The method according to  claim 1 , wherein the electrically conducting layer is a host substrate and placing includes wafer bonding the host substrate to the epitaxial film.  
     
     
         16 . The method according to  claim 1 , wherein the host substrate comprises silicon.  
     
     
         17 . The method according to  claim 1 , and further comprising after step (a): 
 applying an insulating layer over the electrically conductive layer to prevent the etching solution from contacting the conductive layer.    
     
     
         18 . A method for fabricating a light emitting device comprising 
 (a) providing a semiconductor epitaxial layer structure grown on an electrically insulating substrate and capable of producing light emission under an electric bias,    (b) disposing an electrically conductive layer over a first surface of the epitaxial layer structure facing away from the insulating substrate to provide an electric contact with the epitaxial layer structure,    (c) placing the epitaxial layer structure having the conductive layer and the insulating substrate in an etching solution,    (d) applying an electrochemical potential between the epitaxial layer structure and a counter electrode to dissociate a thin etch layer positioned between the epitaxial layer structure and the insulating substrate to thereby separate the epitaxial layer structure and the insulating substrate from each other, and    (e) applying an electric contact to a second surface of the epitaxial layer structure opposite the first surface to provide the electric bias to the epitaxial layer structure.    
     
     
         19 . The method according to  claim 18 , wherein the semiconductor epitaxial layer structure comprises a material selected from the group consisting of GaN, AlN, InN and alloys thereof.  
     
     
         20 . The method according to  claim 18 , wherein the semiconductor epitaxial layer structure is a vertical cavity surface emitting laser (VCSEL) structure having an active layer, the method further including: 
 after step (a), etching from the first surface a plurality of trenches that extend through the active layer to define mesas, wherein the mesas are connected by bridges formed from the electrically conductive layer applied in step (b), and    after step (b), applying an insulating layer over the electrically conductive layer to prevent the etching solution from contacting the conductive layer.    
     
     
         21 . The method according to  claim 20 , and further including disposing a reflector on the second surface to provide feedback for the VCSEL.  
     
     
         22 . The method according to  claim 20 , and further including after step (d), connecting the conductive layer with a heat sink.  
     
     
         23 . The method according to  claim 18 , wherein the electrochemical potential is selected to be greater than the anodization potential of the etch layer and smaller than the anodization potential of the epitaxial layer structure.