Reduced electromigration and stressed induced migration of Cu wires by surface coating

Abstract

The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed.

Having thus described our invention, what we claim as new and desire to secure by Letters Patent is:  
     
         1 . A method for forming conductors with high electromigration resistance comprising the steps of 
 forming a layer of dielectric on a substrate,    forming at least one trench in said layer of dielectric,    forming a metal liner in said trench,    forming a conductor on said metal liner filling said trench,    forming a planarized upper surface of said conductor planar with the upper surface of said layer of dielectric, and    forming a conductive film over said upper surface of said conductor, said conductive film forming a metal to metal metallurgical bond.    
     
     
         2 . The method of  claim 1  wherein said step of forming a conductive film includes the step of forming said conductive film by electroless deposition whereby said upper surface of said conductor is protected from oxidation and corrosion and provides high electromigration resistance and high resistance to thermal stress voiding.  
     
     
         3 . The method of  claim 2  wherein said electroless deposited film has a thickness in the range of 1 to 20 nanometers.  
     
     
         4 . The method of  claim 2  wherein said electroless deposited film has a thickness in the range of 1 to 10 nanometers.  
     
     
         5 . The method of  claim 2  wherein said step of electroless deposition includes the steps of first immersing said substrate in a solution of metal ions whereby a layer of nanoparticles of metal are formed on said upper surface of said conductor, 
 second immersing said substrate in an electroless complexed solution of metal ions and hypophosphite ions whereby a metal-phosphide conductive film is formed on said upper surface of said conductor, and  
 annealing said substrate in one of an inert and reducing atmosphere at a temperature of at least 300° C. for at least 2 hours whereby excellent adhesion is obtained between said conductor and said metal phosphide-conductive film.  
 
     
     
         6 . The method of  claim 5  wherein said step of second immersing is omitted.  
     
     
         7 . The method of  claim 5  wherein said conductive film is selected from the group consisting of CoWP, CoSnP, CoP, Pd, In and W and is in the range from 1 to 20 nm thick.  
     
     
         8 . The method of  claim 2  wherein said step of electroless deposition includes the steps of first immersing said substrate in a solution of metal ions whereby a layer of nanoparticles of metal are formed on the surface of said conductor, 
 second immersing said substrate in an electroless complexed solution of metal ions and dimethylamino borane whereby a layer of metal-boron conductive film is formed on said upper surface of said conductor, and  
 annealing said substrate in one of an inert and reducing atmosphere at a temperature of at least 300° C. for at least 2 hours whereby excellent adhesion is obtained between said conductor and said metal boron conductive film.  
 
     
     
         9 . The method of  claim 1  wherein said conductive film is applied on the surface of said conductor by physical methods such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), evaporation, sputtering and thermal metal interdiffusion.  
     
     
         10 . The method of  claim 9  wherein said conductive film is selected from the group consisting of Pd, In, W and mixtures thereof.  
     
     
         11 . A structure comprising: 
 a layer of dielectric on a substrate,    at least one trench formed in said dielectric on said substrate,    a metal liner formed in said trench,    a conductor on said liner filling said trench,    a planarized upper surface of said conductor with the upper surface of said layer of dielectric, and    a conductive film over said upper surface of said conductor, said conductive film forming a metal to metal chemical and metallurgical bond.    
     
     
         12 . The structure of  claim 11  wherein said conductive film is selected from the group consisting of CoWP, CoSnP, CoP, Pd, CoB, CoSnB, CoWB, In, NiB and W whereby said upper surface of said conductor is protected from oxidation and corrosion.  
     
     
         13 . The structure of  claim 12  wherein said conductive film has a thickness in the range of 1 to 20 nm.  
     
     
         14 . The structure of  claim 12  further including an insulating cap dielectric layer over said conductive film on said conductor and said layer of dielectric.  
     
     
         15 . The structure of  claim 14  wherein said insulating dielectric cap layer is selected from the group consisting of silicon nitride, silicon oxide, insulating compounds of SICOH having dielectric constants less than 3.2, diamond-like carbon, fluorinated diamond like carbon and poly (Arylene ether).  
     
     
         16 . The structure of  claim 11  wherein said conductor is selected from the group consisting of copper and copper alloys.  
     
     
         17 . The structure of  claim 11  wherein said susbtrate is chosen from the group of silicon, silicon-germanium, SOI, and gallium arsenide.  
     
     
         18 . A method for forming conductors with high electromigration resistance comprising the steps of 
 forming a patterned conductor on a substrate,    forming a conductive film over said surface of said conductor, said conductive film forming a metal to metal metallurgical bond.    
     
     
         19 . The method of  claim 18  wherein said step of forming a conductive film includes the step of forming said conductive film by electroless deposition whereby said surface of said conductor is protected from oxidation and corrosion and provides high electromigration resistance and high resistance to thermal stress voiding.  
     
     
         20 . The method of  claim 19  wherein said electroless deposited film has a thickness in the range of 1 to 20 nanometers.  
     
     
         21 . The method of  claim 19  wherein said electroless deposited film has a thickness in the range of 1 to 10 nanometers.  
     
     
         22 . The method of  claim 19  wherein said step of electroless deposition includes the steps of first immersing said substrate in a solution of metal ions whereby a layer of nanoparticles of metal are formed on said surface of said conductor, 
 second immersing said substrate in an electroless complexed solution of metal ions and hypophosphite ions whereby a metal-phosphide conductive film is formed on said surface of said conductor, and  
 annealing said substrate in one of an inert and reducing atmosphere at a temperature of at least 300° C. for at least 2 hours whereby excellent adhesion is obtained between said conductor and said metal phosphide conductive film.  
 
     
     
         23 . The method of  claim 22  wherein said step of second immersing is omitted.  
     
     
         24 . The method of  claim 22  wherein said conductive film is selected from the group consisting of CoWP, CoSnP, CoP, Pd, In and W and is in the range from 1 to 20 nm thick.  
     
     
         25 . The method of  claim 19  wherein said step of electroless deposition includes the steps of first immersing said substrate in a solution of metal ions whereby a layer of nanoparticles of metal are formed on the surface of said conductor, 
 second immersing said substrate in an electroless complexed solution of metal ions and dimethylamino borane whereby a layer of metal-boron conductive film is formed on said surface of said conductor, and  
 annealing said substrate in one of an inert and reducing atmosphere at a temperature of at least 300° C. for at least 2 hours whereby excellent adhesion is obtained between said conductor and said metal boron conductive film.  
 
     
     
         26 . The method of  claim 18  wherein said conductive film is applied on the surface of said conductor by physical methods such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), evaporation, sputtering and thermal metal interdiffusion.  
     
     
         27 . The method of  claim 26  wherein said conductive film is selected from the group consisting of Pd, In, W and mixtures thereof.  
     
     
         28 . A structure comprising: 
 a patterned conductor on a substrate,    a conductive film over said surface of said conductor, said conductive film forming a metal to metal metallurgical bond.    
     
     
         29 . The structure of  claim 28  wherein said conductive film is selected from the group consisting of CoWP, CoSnP, CoP, Pd, CoB, CoSnB, CoWB, In, NiB and W whereby said upper surface of said conductor is protected from oxidation and corrosion.  
     
     
         30 . The structure of  claim 29  wherein said conductive film has a thickness in the range of 1 to 20 nm.  
     
     
         31 . The structure of  claim 29  further including an insulating cap dielectric layer over said conductive film on said conductor.  
     
     
         32 . The structure of  claim 31  wherein said insulating dielectric cap layer is selected from the group consisting of silicon nitride, silicon oxide, insulating compounds of SICOH having dielectric constants less than 3.2, diamond-like carbon, fluorinated diamond like carbon and poly (Arylene ether).  
     
     
         33 . The structure of  claim 29  wherein said conductor is selected from the group consisting of copper and copper alloys.  
     
     
         34 . The structure of  claim 29  wherein said susbtrate is chosen from the group of silicon, silicon-germanium, SOI, and gallium arsenide.  
     
     
         35 . The method of  claim 8  wherein said conductive film is selected from the group consisting of CoB, CoSnB, CoWB and NiB.  
     
     
         36 . The method of  claim 25  wherein said conductive film is selected from the group consisting of CoB, CoSnB, CoWB and NiB.